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Y86-64

ISA

Y86-64 is an instruction set architecture described in the cited formal-verification report through its instruction encodings, instruction families, and processor implementations. Its standard instruction set uses variable-length encodings from one to ten bytes and includes moves, arithmetic/logical operations, conditional branches and moves, calls, returns, and stack operations. The report also presents SEQ, a sequential reference implementation, and PIPE, a five-stage pipelined implementation with several variants used in verification work.

First seen 5/25/2026
Last seen 5/25/2026
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WIKI

Y86-64

Y86-64 is an instruction set architecture described in the cited formal-verification report through its instruction encodings, function-code families, and reference processor implementations. Its standard instruction set includes halt, nop, register and memory moves, arithmetic/logical operations, conditional branches and moves, procedure-call instructions, and stack operations. An iaddq instruction is described separately as optional rather than part of the standard instruction set. [instruction encoding and set]

Instruction encoding and instruction classes

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CITATIONS

12 sources
12 citations — click to expand
[1] instruction encoding and set Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[2] function-code families Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[3] stack and procedure calls Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[4] optional iaddq Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[5] CISC-like features Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[6] RISC-like simplifications Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[7] SEQ implementation Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[8] SEQ cycle flow Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[9] PIPE implementation Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[10] PIPE standard and FULL variants Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[11] PIPE other variants Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[12] verification setup Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5