Recurrent Neural Network Stimulus Generation

Technique

Recurrent Neural Network Stimulus Generation is a coverage-driven hardware verification technique in which an RNN dynamically changes pseudorandom-generator constraints, uses the resulting programs as processor stimuli, and feeds coverage results back into the optimizer to improve subsequent stimulus generation.

First seen 5/28/2026

Last seen 5/28/2026

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Overview

Recurrent Neural Network Stimulus Generation is a feedback-driven test-application technique for hardware verification. In the described approach, a recurrent neural network (RNN) acts as an optimizer that dynamically alters the constraints of a pseudorandom generator during verification. The goal is to improve coverage by using coverage feedback from completed simulations to guide later stimulus generation. [C1]

Verification workflow

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Functional Coverage uses → 90% 1e

The RNN technique uses functional coverage data as its quality function for optimizing stimulus generation.

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CITATIONS

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[1] An RNN-based technique dynamically alters pseudorandom-generator constraints to guide stimulus generation in hardware verification. [PDF] UVM-based verification of RISC-V superscalar processors

[2] The iterative workflow is: RNN changes pseudorandom-generator constraints, the generator creates a program, the simulation runs, and coverage feedback is collected and returned to the optimizer. [PDF] UVM-based verification of RISC-V superscalar processors

[3] The generated processor stimuli were programs loaded directly into processor memory with an approximate length of 100 instructions. [PDF] UVM-based verification of RISC-V superscalar processors

[4] The quality function used coverage analysis data including Functional Coverage, statement coverage, branch coverage, expression coverage, and FSM coverage. [PDF] UVM-based verification of RISC-V superscalar processors

[5] Recurrent Neural Network Stimulus Generation uses Functional Coverage as part of its feedback and scoring mechanism. [PDF] UVM-based verification of RISC-V superscalar processors

[6] Experiments showed a considerable increase in achieved functional coverage, although the default approach appeared more efficient during some initial time. [PDF] UVM-based verification of RISC-V superscalar processors

[7] The broader verification-automation problem is to apply constrained-random or directed sequences to maximize coverage over multiple trials and support autonomous coverage closure with small regression test time. [PDF] UVM-based verification of RISC-V superscalar processors