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Recurrent Neural Network Stimulus Generation

Technique WIKI v1 · 5/28/2026

Recurrent Neural Network Stimulus Generation is a coverage-driven hardware verification technique in which an RNN dynamically changes pseudorandom-generator constraints, uses the resulting programs as processor stimuli, and feeds coverage results back into the optimizer to improve subsequent stimulus generation.

Overview

Recurrent Neural Network Stimulus Generation is a feedback-driven test-application technique for hardware verification. In the described approach, a recurrent neural network (RNN) acts as an optimizer that dynamically alters the constraints of a pseudorandom generator during verification. The goal is to improve coverage by using coverage feedback from completed simulations to guide later stimulus generation. [C1]

Verification workflow

The technique operates as an iterative closed loop:

  1. The RNN optimizer generates changes to the pseudorandom-generator constraints.
  2. The pseudorandom generator creates a processor program stimulus.
  3. The generated program is loaded directly into the processor memory.
  4. The simulation runs on the design under verification.
  5. Coverage feedback is collected after simulation.
  6. The coverage feedback is fed back to the RNN optimizer for the next iteration. [C2]

In the reported use case, the generated stimuli were programs of approximately 100 instructions loaded into processor memory. [C3]

Coverage-driven objective

The quality function for the approach was determined from coverage analysis data. The evidence specifically lists Functional Coverage, statement coverage, branch coverage, expression coverage, and FSM coverage as inputs to the quality function. [C4]

Because Functional Coverage is one of the explicit coverage inputs used to score generated stimuli, this technique uses Functional Coverage as part of its optimization feedback. [C5]

Reported behavior

The cited thesis reports that experiments with the RNN-based constraint-adjustment approach showed a considerable increase in achieved functional coverage. It also notes that, during some initial period, the default approach appeared to be more efficient than the RNN-guided method. [C6]

Role in verification automation

The technique fits into the broader test-application phase of verification automation, where the problem is how to apply available directed or parameterized constrained-random sequences to maximize verification coverage over multiple trials. The evidence frames this as part of autonomous coverage closure with reduced regression test time. [C7]

LINKED ENTITIES

1 links
Functional Coverage USES

CITATIONS

7 sources
7 citations
[1] An RNN-based technique dynamically alters pseudorandom-generator constraints to guide stimulus generation in hardware verification. [PDF] UVM-based verification of RISC-V superscalar processors
[2] The iterative workflow is: RNN changes pseudorandom-generator constraints, the generator creates a program, the simulation runs, and coverage feedback is collected and returned to the optimizer. [PDF] UVM-based verification of RISC-V superscalar processors
[3] The generated processor stimuli were programs loaded directly into processor memory with an approximate length of 100 instructions. [PDF] UVM-based verification of RISC-V superscalar processors
[4] The quality function used coverage analysis data including Functional Coverage, statement coverage, branch coverage, expression coverage, and FSM coverage. [PDF] UVM-based verification of RISC-V superscalar processors
[5] Recurrent Neural Network Stimulus Generation uses Functional Coverage as part of its feedback and scoring mechanism. [PDF] UVM-based verification of RISC-V superscalar processors
[6] Experiments showed a considerable increase in achieved functional coverage, although the default approach appeared more efficient during some initial time. [PDF] UVM-based verification of RISC-V superscalar processors
[7] The broader verification-automation problem is to apply constrained-random or directed sequences to maximize coverage over multiple trials and support autonomous coverage closure with small regression test time. [PDF] UVM-based verification of RISC-V superscalar processors