Pseudo-Random Test-Program Generation

Technique

Pseudo-random test-program generation is an automatic verification technique for microprocessor designs in which test programs are synthesized algorithmically rather than written by hand, typically guided by a verification plan that biases the randomness toward targeted design features. It was applied to functional verification of the x86 microprocessor family, where it was credited with the potential to detect escape bugs such as the Pentium Floating Point bugs.

First seen 6/9/2026

Last seen 6/9/2026

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Pseudo-Random Test-Program Generation

Overview

Pseudo-random test-program generation is a functional verification technique used in microprocessor design verification. Instead of relying on manually authored test cases, an automatic generator synthesizes test programs algorithmically, producing stimuli that exercise a design under verification (DUV) in a pseudo-random fashion. The approach is intended to address the lack of a rigorous, widely adopted methodology for microprocessor verification by automating stimulus creation while still allowing verification engineers to direct the effort.

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graph · pseudo-random test-program generation · depth=1

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Genesys ← implements 1e

Genesys implements pseudo-random test-program generation as an automatic test-program generator.

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Genesys IMPLEMENTS Extracted graph relationship

CITATIONS

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[1] Microprocessor design verification lacked a commonly followed rigorous methodology, motivating the pseudo-random test-program generation approach. Functional verification methodology for microprocessors using the Genesys test-program generator. Application to the x86 microprocessors family (DATE 1999)

[2] Genesys is an automatic pseudo-random test-program generator that promotes the verification methodology. Functional verification methodology for microprocessors using the Genesys test-program generator. Application to the x86 microprocessors family (DATE 1999)

[3] The methodology relies on a verification plan that induces 'smart sets of tests' carrying out the verification tasks. Functional verification methodology for microprocessors using the Genesys test-program generator. Application to the x86 microprocessors family (DATE 1999)

[4] The pseudo-random test-program generation methodology was applied to verify an x86 design. Functional verification methodology for microprocessors using the Genesys test-program generator. Application to the x86 microprocessors family (DATE 1999)

[5] The methodology is described as capable of helping to avoid known escape bugs such as the infamous Pentium Floating Point bugs. Functional verification methodology for microprocessors using the Genesys test-program generator. Application to the x86 microprocessors family (DATE 1999)