Technique
Technique
1259 entities#
1 Delta-Delay Model
3 2 Exhaustive Dynamic Power Capturing
3 3 artifact generation
3 4 CSR-transition coverage metric
3 5 Marching-Sticks Model
3 6 SystemVerilog Constrained-Random Testbench
3 7 On-Device Sequence Generation
3 8 On-Server Sequence Generation
3 9 Class-Based Testbench
3 10 Coverage feedback
3 11 Scope Management
3 12 Random Mutation
3 13 t-probing security
3 14 Tandem Execution
3 15 Single-Class Randomization Architecture
3 16 Hashing-Based Sampling
3 17 ChatFuzz
3 18 Parallelized Fork
3 19 reassembly-based output verification
3 20 Coverage-Guided Hardware-Software Contract Fuzzing
3 21 Hybrid Automata Modeling
3 22 Symbolic Execution for ISA Testing
3 23 Graph Neural Network (GNN)
3 24 Natural Language Processing (NLP)
3 25 Data Path Modeling
3 26 hierarchical constrained-random stimulus generation
3 27 Coverage-Feedback Prompting Template
3 28 Bayesian Network
3 29 Completeness Analysis
3 30 Emulation-Based Fuzzing
3 31 Compiled Simulation
3 32 differential fuzz testing for CPU verification
3 33 Seed Corpus Optimization
3 34 Dependency-Aware Heuristic
3 35 Frequency Heuristic
3 36 Directed Instruction Stream Generation
3 37 Feedback-Adjusted Markov Model
3 38 Sandbox State Protection
3 39 RTL Co-simulation
3 40 Test Stimuli Generation
3 41 Dialogue Restarting
3 42 tree-based branching mutation strategy
3 43 Design Verification
3 44 agile co-verification methodology
3 45 Genetic Algorithm
3 46 RTL Flattening
3 47 Mutation-Based Test Generation
3 48 control register coverage
3 49 RVFI-DII
3 50 Compiler Instrumentation
3 51 Jinja2 Template Engine
3 52 Instruction Injection
3 53 LSTM
3 54 Rule-Based Code Generation
3 55 VM Snapshot Save and Restore
3 56 Pre-Silicon Verification
3 57 Mutational Fuzzing
3 58 multiplexer select coverage
3 59 Genetic Algorithm (GA)
3 60 Graph Compaction and Clustering
3 61 Specification-based Test Generation
3 62 depth-bounded search
3 63 Snapshot-based Fuzzing
3 64 whitebox testing
3 65 template-based test generation
3 66 CP search strategies
3 67 Binary Rewriting
3 68 random regression testing
3 69 Difftest
3 70 Sequence Level Parallelism
3 71 LLM-Assisted RTL Code Generation
3 72 Code Coverage Measurement
3 73 Clausal Reduction Optimization
3 74 hardware-software parallelism (non-blocking transmission)
3 75 TIUP
3 76 Snapshot-Based Testing
3 77 Bi-LSTM
3 78 FPGA-Accelerated Verification
3 79 Instruction Address Correction
3 80 Multi-Class Randomization Architecture
3 81 Random Testing
3 82 DPI Interface
3 83 four-eyes manual classification
3 84 Semantic Level Mutation
3 85 Field Level Mutation
3 86 State Synchronization
3 87 Dynamic Redundant Load Pruning
3 88 Concurrent Multi-Threaded Test-Case Generation
3 89 Template-Based Instruction Generation
3 90 design simulation
3 91 UVM-TLM Co-Simulation
3 92 Simulation-based Functional Verification
3 93 Instruction Coverage Analysis (TSVC)
3 94 Multi-Pass Consistency Checking
3 95 FPGA-Based Fault Injection
3 96 Machine Learning for Fuzzing
3 97 Polynomial Formal Verification (PFV)
3 98 semantics-aware test case generation
3 99 Asynchronous Interrupt Handling
3 100 Dual-Pass Branch Generation
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