Technique
Technique
1157 entities#
1 artifact generation
3 2 Parallelized Fork
3 3 Coverage-Guided Hardware-Software Contract Fuzzing
3 4 Logic Simulation
3 5 Symbolic Execution for ISA Testing
3 6 Data Path Modeling
3 7 Hashing-Based Sampling
3 8 hierarchical constrained-random stimulus generation
3 9 Completeness Analysis
3 10 Compiled Simulation
3 11 Seed Corpus Optimization
3 12 Dependency-Aware Heuristic
3 13 Frequency Heuristic
3 14 Firmware Fuzzing
3 15 Directed Instruction Stream Generation
3 16 Sandbox State Protection
3 17 Coverage-Feedback Prompting Template
3 18 reassembly-based output verification
3 19 Graph Compaction and Clustering
3 20 Test Stimuli Generation
3 21 Dialogue Restarting
3 22 Natural Language Processing (NLP)
3 23 tree-based branching mutation strategy
3 24 Hybrid Automata Modeling
3 25 Feedback-Adjusted Markov Model
3 26 differential fuzz testing for CPU verification
3 27 Mutation-Based Test Generation
3 28 SystemVerilog Constraint Randomization
3 29 RTL Flattening
3 30 Genetic Algorithm (GA)
3 31 Graph Neural Network (GNN)
3 32 RVFI-DII
3 33 Design Verification
3 34 Instruction Injection
3 35 Pre-Silicon Verification
3 36 Genetic Algorithm
3 37 n-gram Language Model
3 38 Exhaustive Dynamic Power Capturing
3 39 Specification-based Test Generation
3 40 Asynchronous Interrupt Handling
3 41 Address-based Coverage Filtering
3 42 Code Coverage Measurement
3 43 template-based test generation
3 44 VM Snapshot Save and Restore
3 45 random regression testing
3 46 Sequence Level Parallelism
3 47 LLM-Assisted RTL Code Generation
3 48 Snapshot-based Fuzzing
3 49 whitebox testing
3 50 Difftest
3 51 hardware-software parallelism (non-blocking transmission)
3 52 Biased Random Test Generation
3 53 CP search strategies
3 54 SystemVerilog Constrained-Random Testbench
3 55 TIUP
3 56 Snapshot-Based Testing
3 57 FPGA-Accelerated Verification
3 58 Clausal Reduction Optimization
3 59 depth-bounded search
3 60 Jinja2 Template Engine
3 61 Instruction Address Correction
3 62 Multi-Class Randomization Architecture
3 63 Bi-LSTM
3 64 Template-Based Instruction Generation
3 65 DPI Interface
3 66 Lockstep Co-Simulation Methodology
3 67 Semantic Level Mutation
3 68 Field Level Mutation
3 69 State Synchronization
3 70 Dynamic Redundant Load Pruning
3 71 four-eyes manual classification
3 72 UVM-TLM Co-Simulation
3 73 Dual-Pass Branch Generation
3 74 Instruction Coverage Analysis (TSVC)
3 75 Off-Platform Floating-Point Operand Pre-Generation
3 76 FPGA-Based Fault Injection
3 77 Polynomial Formal Verification (PFV)
3 78 semantics-aware test case generation
3 79 Machine Learning for Fuzzing
3 80 Concurrent Multi-Threaded Test-Case Generation
3 81 Binary Rewriting
3 82 Hardware Dynamic Information Flow Tracking
3 83 Proxy-Based Fuzzing
3 84 Simulation-based Functional Verification
3 85 ISA-Aware Instruction Generation
3 86 Multi-Pass Consistency Checking
3 87 design simulation
3 88 Rule-Based Code Generation
3 89 optimised instruction set tree traversal
3 90 lazy memory synchronisation
3 91 Taint Liveness Annotation
3 92 ApproxMC
3 93 Interruption and Exception Simulation
3 94 Deep Reinforcement Learning for Test Generation
3 95 Hardware-Based Mutation
3 96 Exception Stimulus Generation
3 97 Asynchronous Event Stimulus
3 98 Input Instruction Distillation
3 99 Variant of Ant Colony Optimization
3 100 Hierarchical Constrained-Random Test Generation
3