Rule-Based Code Generation

Technique

First seen 7/12/2026

Last seen 7/12/2026

Evidence 3 chunks

NEIGHBORHOOD

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3 connections

HAVEN ← uses 99% 3e

HAVEN delegates all code generation to a rule-based CodeGen that guarantees SystemVerilog syntactic correctness.

SystemVerilog implements → 97% 2e

The rule-based CodeGen translates DSL steps into protocol-correct SystemVerilog code.

UVM Sequence implements → 97% 2e

Rule-based CodeGen translates DSL JSON documents into protocol-correct UVM sequence code.