Compiled simulation is a simulator implementation technique, especially described for instruction set simulators, in which instruction decoding—and sometimes static scheduling—is moved to compile time. This can improve runtime performance by avoiding the decode bottleneck of interpretive simulation, but it is not applicable to run-time modifiable code or dynamic scheduling. Related work also uses the term for compiled hardware-description-language simulation, such as Verilog flow-graph machine-code simulators.

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