Overview

Compiled simulation is described in instruction set simulation as one of three main paradigms, alongside interpretive simulation and just-in-time compiled simulation (JIT-CS). These paradigms differ in their flexibility and performance characteristics. [Compiled simulation taxonomy]

Execution model

In compiled simulation, the simulator performs instruction decoding at compile time. In some cases, it can also perform static scheduling at compile time. This contrasts with interpretive simulation, where instructions are decoded one by one during execution and instruction decoding is identified as the bottleneck. [Compile-time decoding]

Trade-offs

The main limitation stated for compiled simulation is applicability: it is not applicable for run-time modifiable code or for dynamic scheduling. JIT-CS is presented as an approach that attempts to combine advantages of interpretive and compiled approaches by storing information about previously decoded instructions in a cache and reusing it when the same instruction executes again. [Applicability limits and JIT comparison]

Performance context

Evidence from instruction set simulator work frames compiled simulation as a high-performance point in the simulator design space. In one reported comparison for a small pipelined processor, an interpretive simulator achieved 0.22 MIPS, a just-in-time compiled simulator achieved 14 MIPS, and an ISS generated from a property suite achieved 7 MIPS, described as outperforming interpretive simulation and reaching about 50% of a state-of-the-art JIT-CS tool. [ISS performance comparison]

Use beyond instruction set simulation

The term is also used in hardware-description-language simulation. A public arXiv summary for the CVC Verilog Compiler describes development of Verilog HDL optimized flow-graph compiled simulators, including compilation toward machine-code sequences intended to exploit modern processor low-level parallelism. [Compiled Verilog simulation]

Role in simulator design

Within instruction set simulation, compiled simulation emphasizes moving decode work out of runtime. The relevant design choice is characterized as a balance between flexibility and performance: interpretive simulators provide high flexibility for run-time modifiable programs, compiled simulators shift decoding and sometimes scheduling to compile time, and JIT-CS caches decoded-instruction information to approach compiled-simulation performance while retaining interpretive flexibility. [Flexibility-performance trade-off]