Technique
Technique
1157 entities#
1 failure cause analysis
3 2 differential fuzz testing for CPU verification
3 3 Interruption and Exception Simulation
3 4 CSR-transition coverage metric
3 5 hardware-software parallelism (non-blocking transmission)
3 6 Genetic Algorithm (GA)
3 7 SystemVerilog Constraint Randomization
3 8 Constraint-Based Stimulus Generation
3 9 LLM-Assisted RTL Code Generation
3 10 Coverage feedback
3 11 Hardware-Based Mutation
3 12 Input Instruction Distillation
3 13 cross-entropy loss for sequence generation
3 14 Variant of Ant Colony Optimization
3 15 Design Verification
3 16 Positive and Negative Test Generation
3 17 Hierarchical Constrained-Random Test Generation
3 18 template-based test generation
3 19 Random Binary Generation
3 20 Specification-based Test Generation
3 21 Bi-LSTM
3 22 Coverage-Feedback Prompting Template
3 23 Firmware Fuzzing
3 24 Simulation-based Functional Verification
3 25 Pre-Silicon Verification
3 26 Multi-Class Randomization Architecture
3 27 cell-level taint instrumentation
3 28 TIUP
3 29 RVFI-DII
3 30 static design analysis
3 31 Single-Class Randomization
3 32 Dialogue Restarting
3 33 Test Stimuli Generation
3 34 RTL Flattening
3 35 tree-based branching mutation strategy
3 36 Mutation-Based Test Generation
3 37 Bug Injection
3 38 Lockstep Co-Simulation Methodology
3 39 Genetic Algorithm
3 40 Composite Current Source Models
2 41 mispredicted path fuzzing
2 42 Register Value Comparison
2 43 Bitflip Mutation
2 44 TLM Fifo Asynchronous Communication
2 45 VIP Level Parallelism
2 46 Asynchronous Worker Threads
2 47 Lazy Merging of Directed Streams
2 48 Profiling
2 49 hardware prototyping
2 50 Transaction Level Modeling
2 51 Discrete Event Simulation
2 52 Inter-Process Communication
2 53 Instruction Generation
2 54 user-assisted code generation
2 55 Object-Oriented Constraint Partitioning
2 56 Maintain-Arc-Consistency
2 57 Constraint-Based Branch Stimulus Generation
2 58 pseudorandom generator (PRG)
2 59 recurrent neural network-based constraint alteration
2 60 Pseudorandom Generator (PRG) Stimulus Generation
2 61 retirement-level lockstep co-simulation
2 62 Hardware-based Mutation Strategies
2 63 blacklisting instructions
2 64 Constraint Propagation
2 65 architectural state comparison at instruction retirement
2 66 Directed Random Stimuli Generation
2 67 unified coverage methodology
2 68 Stateless Model Checking
2 69 Simulation-based Processor Verification
2 70 Symbolic Execution for Test Generation
2 71 Endless Instruction Stream Generation
2 72 Post-processing Test Vector Clustering
2 73 Arithmetic Mutation
2 74 Dynamic Program Analysis
2 75 Signature File Comparison
2 76 Object-Oriented Verification
2 77 Dedicated DFI Cache
2 78 instruction field mutation
2 79 post-processing trace analysis
2 80 opcode injection
2 81 pseudo-random test-program generation
2 82 Virtual Coverage
2 83 UVM testbench
2 84 object-oriented constraint-based instruction generation
2 85 Bottom-Up Implementation
2 86 Supervised Learning
2 87 Counterexample-Driven Development
2 88 Sequence Import/Export
2 89 labeling phase
2 90 positive and negative testing
2 91 Coverage-guided Aging Counter
2 92 Randomized Test Strategy
2 93 Cross-product Coverage Points
2 94 Divide-and-Conquer Strategy
2 95 Automated Test Case Reduction
2 96 Model-Based Random Testing
2 97 context-free grammar specification with annotations
2 98 overlapping template composition
2 99 Constraint Logic Programming
2 100 automated translation from architecture specifications
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