Random Binary Generation

Technique

Random Binary Generation is a verification technique used in the cited RISC-V vector accelerator project to create constrained-random RISC-V assembly tests/binaries with RISCV-DV, adapt them for RVV 0.7.1 vector instruction testing, and run them through an automated UVM, Spike co-simulation, and CI/CD regression flow.

First seen 5/27/2026

Last seen 5/28/2026

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Random Binary Generation

Definition

In the referenced RISC-V vector accelerator verification work, Random Binary Generation refers to creating random or constrained-random RISC-V assembly tests/binaries and using them as executable stimulus for functional verification. The project used the RISCV-DV generator, described in the paper as a Google-developed tool that generates random RISC-V assembly tests, to provide vector instructions to the Vector Processing Unit (VPU). [C1]

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Functional Verification of a RISC-V Vector Accelerator ← uses 95% 3e

Random binary generation is used via RISCV-DV to create test programs.

riscv-dv ← implements 90% 1e

RISCV-DV is used to create random binaries as part of the verification flow.

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Functional Verification of a RISC-V Vector Accelerator USES Extracted graph relationship

CITATIONS

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6 citations — click to expand

[1] RISCV-DV was used to generate random RISC-V assembly tests that provided vector instructions to the VPU. Functional Verification of a RISC-V Vector Accelerator

[2] Random binaries using the RISCV-DV generator complemented the UVM environment and CI infrastructure; automated constrained-random generation, simulation, error reporting, and CI/CD contributed to finding 3005 errors and reaching 95.79% functional coverage. Functional Verification of a RISC-V Vector Accelerator

[3] Spike executed scalar instructions, provided vector instructions to the UVM environment in program order, and supplied reference results for comparison against VPU results. Functional Verification of a RISC-V Vector Accelerator

[4] The project adapted RISCV-DV because it implemented a later RVV version than 0.7.1, adding vsetvli generation, memory-generation changes, data-page initialization selection, memory-address constraints, and RVV 0.7.1 adaptation. Functional Verification of a RISC-V Vector Accelerator

[5] The team initially blacklisted many generated-test instructions while modules were under development and gradually removed them as errors were fixed. Functional Verification of a RISC-V Vector Accelerator

[6] The nightly random-test regression ran 24 tests per night from April to July, then 50 per night from August to late November; each test contained approximately 500 vector instructions. Functional Verification of a RISC-V Vector Accelerator