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Random Binary Generation

Technique WIKI v1 · 5/27/2026

Random Binary Generation is a verification technique used in the cited RISC-V vector accelerator project to create constrained-random RISC-V assembly tests/binaries with RISCV-DV, adapt them for RVV 0.7.1 vector instruction testing, and run them through an automated UVM, Spike co-simulation, and CI/CD regression flow.

Random Binary Generation

Definition

In the referenced RISC-V vector accelerator verification work, Random Binary Generation refers to creating random or constrained-random RISC-V assembly tests/binaries and using them as executable stimulus for functional verification. The project used the RISCV-DV generator, described in the paper as a Google-developed tool that generates random RISC-V assembly tests, to provide vector instructions to the Vector Processing Unit (VPU). [C1]

Role in the verification flow

Random binaries complemented a reusable and extendable UVM verification environment that implemented the protocol between the Open Vector Interface (OVI) and the VPU and checked completed instruction correctness. The random-binary flow was part of a broader infrastructure including constrained-random test generation, simulation, error reporting, and CI/CD. [C2]

The paper’s verification infrastructure also used Spike as a reference model and scalar-core-like executor: Spike executed scalar instructions, provided vector instructions to the UVM environment in program order, and returned reference results for comparison against the device under test. [C3]

RISCV-DV adaptations

The project’s VPU implemented RVV version 0.7.1, while the available RISCV-DV support targeted a later RVV version. The authors therefore adapted RISCV-DV to fit their needs. Reported additions included: [C4]

  • Generating vsetvli instructions through the code.
  • Modifying memory-operation generation so element width and vector length could change.
  • Adding an option to select the initialization pattern of data pages.
  • Constraining memory addresses accessed by tests to avoid memory exceptions, especially for vector indexed memory instructions.
  • Adapting the generator to RVV 0.7.1.

Instruction blacklisting during bring-up

Because some design modules were under development for much of the verification process, the team initially blacklisted many instructions in generated tests so that each iteration could still produce functional tests. As errors were fixed, instructions were gradually removed from the blacklist until all implemented instructions were enabled. [C5]

Regression scale and observed outcome

The paper reports that the team ran 24 random tests every night between April and July, then increased to 50 nightly tests from August through the end of November before RTL freeze. Each test contained approximately 500 vector instructions. Across the process, the verification effort found 3005 errors and reached 95.79% functional coverage. [C6]

Practical purpose

Within this project, Random Binary Generation served as a way to continuously exercise the vector accelerator with varied instruction streams, integrate those tests into CI, and support coverage closure. The paper specifically attributes the verification results to automated constrained-random test generation, simulation and error reporting, and CI/CD infrastructure. [C2]

LINKED ENTITIES

1 links
Functional Verification of a RISC-V Vector Accelerator USES

CITATIONS

6 sources
6 citations
[1] RISCV-DV was used to generate random RISC-V assembly tests that provided vector instructions to the VPU. Functional Verification of a RISC-V Vector Accelerator
[2] Random binaries using the RISCV-DV generator complemented the UVM environment and CI infrastructure; automated constrained-random generation, simulation, error reporting, and CI/CD contributed to finding 3005 errors and reaching 95.79% functional coverage. Functional Verification of a RISC-V Vector Accelerator
[3] Spike executed scalar instructions, provided vector instructions to the UVM environment in program order, and supplied reference results for comparison against VPU results. Functional Verification of a RISC-V Vector Accelerator
[4] The project adapted RISCV-DV because it implemented a later RVV version than 0.7.1, adding vsetvli generation, memory-generation changes, data-page initialization selection, memory-address constraints, and RVV 0.7.1 adaptation. Functional Verification of a RISC-V Vector Accelerator
[5] The team initially blacklisted many generated-test instructions while modules were under development and gradually removed them as errors were fixed. Functional Verification of a RISC-V Vector Accelerator
[6] The nightly random-test regression ran 24 tests per night from April to July, then 50 per night from August to late November; each test contained approximately 500 vector instructions. Functional Verification of a RISC-V Vector Accelerator