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TIUP

Technique

TIUP is a processor formal-verification technique introduced in the paper “TIUP: Effective Processor Verification with Tautology-Induced Universal Properties.” It uses tautologies as universal properties and abstract specifications to cover processor data and control paths, aiming to reduce verification difficulty compared with approaches relying on a single self-consistency universal property.

First seen 5/26/2026
Last seen 5/26/2026
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Overview

TIUP is a technique for effective processor verification using tautology-induced universal properties. It was introduced to address challenges in formal verification of large and intricate processor designs, where verification is described as complex, costly, and demanding in terms of labor and expertise for property formulation. [C1]

The technique uses tautologies as universal properties. In the cited abstract, these tautologies are described as abstract specifications that can cover processor data paths and control paths. [C2]

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RELATIONSHIPS

6 connections
tautology-induced universal properties implements → 100% 3e
TIUP is built upon the concept of using tautologies as universal properties for verification.
Self-Consistency Universal Property ← compares with 95% 3e
TIUP is proposed to address the limitations of the single self-consistency universal property, such as false positives and scalability issues.
TIUP: Effective Processor Verification with Tautology-Induced Universal Properties ← introduces 100% 2e
The paper presents TIUP as a novel technique for processor verification using tautologies as universal properties.
abstract specification uses → 100% 2e
TIUP uses tautologies as abstract specifications to cover processor data and control paths.
processor data path verification ← part of 95% 2e
TIUP covers processor data paths as part of its verification scope.
processor control path verification ← part of 95% 2e
TIUP covers processor control paths as part of its verification scope.

LINKED ENTITIES

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Self-Consistency Universal Property contrasts_with The evidence says prior research used a single self-consistency universal property, but it faced false positives and scalability issues that TIUP was introduced to tackle.

CITATIONS

7 sources
7 citations — click to expand
[1] TIUP is introduced as a processor-verification technique in the paper “TIUP: Effective Processor Verification with Tautology-Induced Universal Properties.” TIUP: Effective Processor Verification with Tautology-Induced Universal Properties
[2] TIUP uses tautologies as universal properties and as abstract specifications covering processor data and control paths. TIUP: Effective Processor Verification with Tautology-Induced Universal Properties
[3] Formal verification is described as useful for thoroughly examining design behaviors but requiring extensive labor and expertise in property formulation. TIUP: Effective Processor Verification with Tautology-Induced Universal Properties
[4] A single self-consistency universal property is reported to face false positives and scalability issues due to exponential state-space growth. TIUP: Effective Processor Verification with Tautology-Induced Universal Properties
[5] TIUP is intended to simplify and streamline verification for engineers and enable efficient formal processor verification. TIUP: Effective Processor Verification with Tautology-Induced Universal Properties
[6] The arXiv record lists authors Yufeng Li, Yiwei Ci, and Qiusong Yang, arXiv identifier 2404.17094, arXiv DOI 10.48550/arXiv.2404.17094, and related DOI 10.1109/ASP-DAC58780.2024.10473912. TIUP: Effective Processor Verification with Tautology-Induced Universal Properties
[7] The arXiv page states that the work was accepted by ASP-DAC 2024, is not the final camera-ready version, and is categorized under Logic in Computer Science, Hardware Architecture, and Systems and Control. TIUP: Effective Processor Verification with Tautology-Induced Universal Properties