Multi-Class Randomization Architecture — STIMSMITH

Multi-Class Randomization Architecture

Technique

Multi-Class Randomization Architecture is a constrained-random instruction-generation technique that reduces solver problem size by splitting a monolithic opcode class into a base instruction class plus opcode-category child classes. In the cited AMD/Synopsys microcode-stimulus generator, the approach preserved distribution and test-level control while improving runtime and memory relative to a single-class constrained-random implementation.

First seen 5/25/2026

Last seen 5/25/2026

Evidence 3 chunks

Wiki v1

WIKI

Overview

Multi-Class Randomization Architecture is a hierarchical constrained-random technique for generating microcode or opcode stimuli. It was described as an alternative to both serial field randomization and a monolithic single-class constrained-random opcode model. The technique first chooses an opcode category and then randomizes a category-specific class, so the constraint solver only sees the constraints relevant to that category. [Multi-class decomposition] [Performance conclusion]

Problem Addressed

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LINKED ENTITIES

1 links

Synopsys VCS Constraint Solver implemented_with The evidence describes the hierarchical constrained-random approach as using the Synopsys VCS constraint solver and discusses VCS profiling and solver behavior.

CITATIONS

12 sources

12 citations — click to expand

[1] Serial randomization limitation Generating AMD microcode stimuli using VCS constraint solver

[2] Single-class baseline Generating AMD microcode stimuli using VCS constraint solver

[3] Two-layer generator architecture Generating AMD microcode stimuli using VCS constraint solver

[4] Multi-class decomposition Generating AMD microcode stimuli using VCS constraint solver

[5] Category-first allocation Generating AMD microcode stimuli using VCS constraint solver

[6] Wrapper-class consideration Generating AMD microcode stimuli using VCS constraint solver

[7] Constraint profiling Generating AMD microcode stimuli using VCS constraint solver

[8] BDD solver context Generating AMD microcode stimuli using VCS constraint solver

[9] Runtime results Generating AMD microcode stimuli using VCS constraint solver

[10] Memory results Generating AMD microcode stimuli using VCS constraint solver

[11] Performance analysis Generating AMD microcode stimuli using VCS constraint solver

[12] Performance conclusion Generating AMD microcode stimuli using VCS constraint solver