Instruction Generation

Technique

Instruction Generation is represented in the evidence by RISCV-DV, an open-source SystemVerilog/UVM instruction generator for RISC-V processor verification. RISCV-DV generates random and directed instruction streams, supports multiple RISC-V ISA profiles and privilege modes, and integrates with simulation, coverage, debug, trap/interrupt, MMU, and ISS co-simulation flows.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

Instruction Generation, in the provided evidence, refers to the generation of instruction streams for processor verification. The concrete implementation described is RISCV-DV, a SystemVerilog/UVM-based open-source instruction generator for RISC-V processor verification. [C1]

Supported RISC-V scope

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NEIGHBORHOOD

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RELATIONSHIPS

1 connections

riscv-dv ← implements 1e

RISCV-DV implements the instruction generation technique.

LINKED ENTITIES

2 links

riscv-dv implemented_by The evidence explicitly identifies RISCV-DV as a SystemVerilog/UVM-based open-source instruction generator for RISC-V processor verification.

chipsalliance project_contributed_to The evidence states that RISC-V DV has been contributed to CHIPS Alliance.

CITATIONS

16 sources

16 citations — click to expand

[1] C1: RISCV-DV is a SystemVerilog/UVM-based open-source instruction generator for RISC-V processor verification. chipsalliance/riscv-dv

[2] C2: RISCV-DV supports RV32IMAFDC and RV64IMAFDC, and supports machine, supervisor, and user privileged modes. chipsalliance/riscv-dv

[3] C3: RISCV-DV supports page-table randomization and exception generation. chipsalliance/riscv-dv

[4] C4: RISCV-DV supports privileged CSR setup randomization and a privileged CSR test suite. chipsalliance/riscv-dv

[5] C5: RISCV-DV supports trap and interrupt handling. chipsalliance/riscv-dv

[6] C6: RISCV-DV includes a test suite to stress test the MMU. chipsalliance/riscv-dv

[7] C7: RISCV-DV supports sub-program generation and random program calls. chipsalliance/riscv-dv

[8] C8: RISCV-DV supports illegal instruction and HINT instruction generation. chipsalliance/riscv-dv

[9] C9: RISCV-DV supports random forward and backward branch instructions. chipsalliance/riscv-dv

[10] C10: RISCV-DV supports mixing directed instructions with a random instruction stream. chipsalliance/riscv-dv

[11] C11: RISCV-DV supports debug mode with a fully randomized debug ROM. chipsalliance/riscv-dv

[12] C12: RISCV-DV provides an instruction-generation coverage model, handshake communication with a testbench, and support for handcoded assembly tests. chipsalliance/riscv-dv

[13] C13: RISCV-DV supports co-simulation with multiple ISS implementations: Spike, riscv-ovpsim, Whisper, and sail-riscv. chipsalliance/riscv-dv

[14] C14: Running RISCV-DV requires an RTL simulator supporting SystemVerilog and UVM 1.2, and the generator has been verified with Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa, and Aldec Riviera-PRO. chipsalliance/riscv-dv

[15] C15: The RISCV-DV source can be cloned from the repository, and the evidence describes direct python3 script usage for developers and editable Python package installation for normal users. chipsalliance/riscv-dv

[16] C16: RISC-V DV has been contributed to CHIPS Alliance, has regular meetings for project discussion, and is not an officially supported Google product. chipsalliance/riscv-dv