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Instruction Generation

Technique WIKI v1 · 5/26/2026

Instruction Generation is represented in the evidence by RISCV-DV, an open-source SystemVerilog/UVM instruction generator for RISC-V processor verification. RISCV-DV generates random and directed instruction streams, supports multiple RISC-V ISA profiles and privilege modes, and integrates with simulation, coverage, debug, trap/interrupt, MMU, and ISS co-simulation flows.

Overview

Instruction Generation, in the provided evidence, refers to the generation of instruction streams for processor verification. The concrete implementation described is RISCV-DV, a SystemVerilog/UVM-based open-source instruction generator for RISC-V processor verification. [C1]

Supported RISC-V scope

RISCV-DV supports the following instruction-set profiles: RV32IMAFDC and RV64IMAFDC. It also supports RISC-V privileged execution in machine mode, supervisor mode, and user mode. [C2]

Generation capabilities

RISCV-DV includes a broad set of instruction-generation capabilities for verification stimulus. These include:

  • Page-table randomization and exception generation. [C3]
  • Privileged CSR setup randomization and a privileged CSR test suite. [C4]
  • Trap and interrupt handling. [C5]
  • MMU stress testing. [C6]
  • Sub-program generation and random program calls. [C7]
  • Illegal instruction and HINT instruction generation. [C8]
  • Random forward and backward branch instructions. [C9]
  • Mixing directed instructions with a random instruction stream. [C10]
  • Debug-mode support using a fully randomized debug ROM. [C11]

Verification-flow integration

RISCV-DV provides an instruction-generation coverage model and handshake communication with a testbench. It also supports handcoded assembly tests. [C12]

For co-simulation, RISCV-DV supports multiple instruction set simulators: Spike, riscv-ovpsim, Whisper, and sail-riscv. [C13]

Tooling requirements

Running the generator requires an RTL simulator that supports SystemVerilog and UVM 1.2. The evidence states that RISCV-DV has been verified with Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa, and Aldec Riviera-PRO simulators. [C14]

Source and usage model

The source can be obtained by cloning the RISCV-DV repository. The evidence describes two usage styles: running scripts directly with python3, which is recommended for developers working across multiple clones, and installing the Python package in editable user mode for normal users. [C15]

Project status

The evidence states that RISC-V DV has been contributed to CHIPS Alliance and that the project holds regular meetings to discuss issues, feature priorities, and development progress. It also notes that the project is not an officially supported Google product. [C16]

LINKED ENTITIES

2 links
riscv-dv implemented_by
chipsalliance project_contributed_to

CITATIONS

16 sources
16 citations
[1] C1: RISCV-DV is a SystemVerilog/UVM-based open-source instruction generator for RISC-V processor verification. chipsalliance/riscv-dv
[2] C2: RISCV-DV supports RV32IMAFDC and RV64IMAFDC, and supports machine, supervisor, and user privileged modes. chipsalliance/riscv-dv
[3] C3: RISCV-DV supports page-table randomization and exception generation. chipsalliance/riscv-dv
[4] C4: RISCV-DV supports privileged CSR setup randomization and a privileged CSR test suite. chipsalliance/riscv-dv
[5] C5: RISCV-DV supports trap and interrupt handling. chipsalliance/riscv-dv
[6] C6: RISCV-DV includes a test suite to stress test the MMU. chipsalliance/riscv-dv
[7] C7: RISCV-DV supports sub-program generation and random program calls. chipsalliance/riscv-dv
[8] C8: RISCV-DV supports illegal instruction and HINT instruction generation. chipsalliance/riscv-dv
[9] C9: RISCV-DV supports random forward and backward branch instructions. chipsalliance/riscv-dv
[10] C10: RISCV-DV supports mixing directed instructions with a random instruction stream. chipsalliance/riscv-dv
[11] C11: RISCV-DV supports debug mode with a fully randomized debug ROM. chipsalliance/riscv-dv
[12] C12: RISCV-DV provides an instruction-generation coverage model, handshake communication with a testbench, and support for handcoded assembly tests. chipsalliance/riscv-dv
[13] C13: RISCV-DV supports co-simulation with multiple ISS implementations: Spike, riscv-ovpsim, Whisper, and sail-riscv. chipsalliance/riscv-dv
[14] C14: Running RISCV-DV requires an RTL simulator supporting SystemVerilog and UVM 1.2, and the generator has been verified with Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa, and Aldec Riviera-PRO. chipsalliance/riscv-dv
[15] C15: The RISCV-DV source can be cloned from the repository, and the evidence describes direct python3 script usage for developers and editable Python package installation for normal users. chipsalliance/riscv-dv
[16] C16: RISC-V DV has been contributed to CHIPS Alliance, has regular meetings for project discussion, and is not an officially supported Google product. chipsalliance/riscv-dv