2026-07-06
6 items 267 entities 309 connections
Processed 48 entities and 50 relations.
RISC-V UVM SystemVerilog Constrained-Random Stimulus Generation Coverage-Driven Verification Directed Testing Assertion-Based Verification Functional Coverage UVM Sequence UVM Sequencer UVM Driver UVM Monitor UVM Scoreboard UVM Coverage Collector Instruction Fetch Unit Instruction Decode Unit ALU Load-Store Unit Register File Control and Status Registers Pipeline and Hazard Unit Interrupt and Exception Unit Branch Prediction Unit Spike ISA Simulator RISCV-DV ModelSim QuestaSim VCS Visual Studio Code Reference Model RTL System on Chip TLM Co-Simulation Regression Testing SystemVerilog Assertions Integrated UVM-TLM Co-Simulation for RISC-V Verification Survey of Verification of RISC-V Processors UVM Verification of RISC-V Instruction Set RISC-V UVM Verification Thesis System-Level Verification of Multi-Core RISC-V CORE-V-VERIF OpenHW Group Nithyashree S Monisha J K M G Jatin Dr. Ambedkar Institute of Technology UVM Agent Random Instruction Generator
Processed 15 entities and 16 relations.
Processed 44 entities and 44 relations.
RISC-V Instruction Set Architecture Automated Test Generation Constrained Random Verification AI Planning Algorithm Synthesis Test Suite Synthesis Custom Instruction Verification Compliance Assurance Core Integrity Verification SoC Integrity Verification Concurrent Test Execution Page Based Virtual Memory Testing Memory Management Unit Cache Coherency MOESI Cache States Atomic Operations Testing Dekker Memory Ordering False-Share Memory Stress Testing Architectural Compliance Testing Firmware-First Testing Power Management Verification Security Verification Performance-Power Profiling End-to-End Use Case Testing Multi-Core Verification Test Graph AXI Wrap Transactions Coherent Mesh Network DDR Memory Model Verification Breker SystemVIP Library Core Integrity FastApps RISC-V System Integrity TrekApp ARM System Integrity TrekApp Cache Coherency TrekApp 2.0 Firmware-First TrekApp Power Management TrekApp Security TrekApp Networking TrekApp Breker Verification Systems RISC-V International Adnan Hamid trek_microloop_write_check8 RV64 Architecture Single Core Multi-Thread Testing
Processed 28 entities and 44 relations.
TestRIG CHERI RISC-V Constrained Random Instruction Generation Security-Aware Instruction Stream Post-Processing Direct Instruction Injection RISC-V Formal Interface Sail RISC-V Formal Model Virtual Prototype In-Memory Computing Capability-Based Memory Protection Tagged Memory RTL Simulation CHERI Early Benchmarks RISC-V VP Security-Aware Benchmarks for Performance Exploration of CHERI-Enabled Architectures Spandan Das Sayak Deb Khushboo Qayyum Sallar Ahmadi-Pour Christoph Luth Rolf Drechsler University of Bremen DFKI Benchmark Suite Design Space Exploration Memory Safety Instruction Stream Generation
Processed 60 entities and 61 relations.
μCFI: Formal Verification of Microarchitectural Control-flow Integrity Katharina Ceesay-Seitz Flavien Solt Kaveh Razavi ETH Zurich Microarchitectural Control-Flow Integrity (μCFI) Constant-Time (CT) execution Control-Flow Integrity (CFI) Register Transfer Level (RTL) Information Flow Tracking (IFT) Formal Property Verification (FPV) taint tracking Program Counter (PC) Instruction Under Verification (IUV) microarchitectural control flow (μCF) declassification of legal flows Instruction Operand Constraint (IOC) taint injection hardware fuzzing timing side-channel attack data-independent execution latency logic abstraction model checking non-influencing (ni) instructions control-influencing (ci) instructions value-influencing (vi) instructions forwarding paths RISC-V ISA pipeline CPU architecture General-Purpose Register (GPR) Control and Status Register (CSR) instruction word (IW) CellIFT CellDFT Jasper FPV Yosys Cascade CPU fuzzer SystemVerilog Assertions (SVA) precise taint injection data flow tracking (DFT) cell-level taint instrumentation static design analysis logic gate shadow logic instrumentation (GLIFT) RTLIFT μCFI verification toolchain Kronos RISC-V CPU PicoRV32 RISC-V CPU Ibex RISC-V CPU Scarv RISC-V CPU unbounded instruction sequence verification hardware security vulnerability CVE (Common Vulnerabilities and Exposures) control-flow hijack delay injection attack formal verification register file instruction operand shadow logic multiplexer select signal RISC-V Data-Independent Execution Latency (DIEL) mode
µArchiFI: Formal Modeling and Verification Strategies for Microarchitectural Fault Injections
source →Processed 72 entities and 94 relations.
μARCHIFI Yosys Fault Injection Microarchitectural Fault Model Faulty Transition System Hardware Transition System Bounded Model Checking Attacker Model Sandboxing Concretization RTL RTLIL Reachability Property SW/HW Co-verification Program Counter Bit-flip Fault Effect Equivalence Checking Formal Verification Prefetch Buffer Pipeline Forwarding Mechanism Synchronous Digital Circuit AIGER SMV BTOR2 SMT-LIB Differential Fault Analysis SystemVerilog Assertion VCD Waveform Trace AES Key Schedule Clock Glitch Electromagnetic Pulse Laser Fault Injection PONO BTORMC YOSYS-BMC FIVER SYNFI VerFI Lazart ARMORY Cadence JasperGold Synopsys VC Formal Siemens QuestaVerify nuXmv SimpliFI SAMVA FaultRTLIL μARCHIFI: Formal Modeling and Verification Strategies for Microarchitectural Fault Injections Simon Tollec Mihail Asavoae Damien Couroussé Karine Heydemann Mathieu Jan CEA List Thales DIS OpenHW Group LowRISC RISC-V CV32E40P Ibex VerifyPIN FISSC Benchmark RV32IMC Verilog Binary Program Lockstep Core Tiny AES SMT Solver Combinational Function Register Transition Function Model Checking