Capability-Based Memory Protection

Concept

A hardware memory-safety approach in which conventional pointers are replaced by capabilities that carry bounds, permissions, and validity metadata, enforced in hardware through a separate non-addressable tagged memory. CHERI for RISC-V is the most prominent implementation, providing fine-grained spatial and temporal memory safety for memory-unsafe languages such as C and C++.

First seen 7/6/2026

Last seen 7/6/2026

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Capability-Based Memory Protection

Definition

Capability-based memory protection is a hardware-supported memory safety paradigm in which every pointer (a capability) carries not only an address but also metadata describing the memory region it is authorized to access. Hardware checks on every load, store, and instruction fetch consult this metadata, providing fine-grained enforcement of spatial and temporal memory safety even in programs written in memory-unsafe languages such as C and C++. ^[1]

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Security-Aware Instruction Stream Post-Processing ← uses 95% 2e

The post-processing ensures proper capability preparation and usage according to CHERI rules.

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CITATIONS

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[1] Capability-based memory protection provides hardware-enforced spatial and temporal memory safety for programs written in memory-unsafe languages such as C and C++. Security-Aware Benchmarks for Performance Exploration of CHERI

[2] In capability-based systems, conventional pointers are replaced with capabilities that encode bounds, permissions, and validity metadata for memory regions. Security-Aware Benchmarks for Performance Exploration of CHERI

[3] Capability tags are propagated through registers, caches, and memory, and are stored in a separate, non-addressable tagged memory accessible only via capability-specific instructions. Security-Aware Benchmarks for Performance Exploration of CHERI

[4] Any illegal manipulation invalidates the capability tag and prevents further memory access through the corrupted capability. Security-Aware Benchmarks for Performance Exploration of CHERI

[5] CHERI is the most mature capability-based memory safety architecture, providing fine-grained enforcement of pointer bounds and permissions in hardware. Security-Aware Benchmarks for Performance Exploration of CHERI

[6] CHERI has been implemented and evaluated across software-based emulation, FPGA prototypes, and ASICs. Security-Aware Benchmarks for Performance Exploration of CHERI

[7] During capability store instructions such as sc.ddc and sc.cap, the corresponding tag bit must be updated alongside the data, which in a conventional implementation requires transferring the tag-containing memory word to the processor, modifying the tag, and writing it back. Security-Aware Benchmarks for Performance Exploration of CHERI

[8] CHERI enforces strict bounds, permission, and validity checks on memory accesses; without properly prepared capabilities, generated memory operations fail and never reach the tagged memory. Security-Aware Benchmarks for Performance Exploration of CHERI

[9] Related hardware memory-safety mechanisms include SoftBound, ARM Memory Tagging Extension, and Intel Memory Protection Extensions. Security-Aware Benchmarks for Performance Exploration of CHERI

[10] Capability-based protection introduces additional metadata handling and memory accesses that can affect performance and energy efficiency in embedded systems. Security-Aware Benchmarks for Performance Exploration of CHERI

[11] Raw instruction streams generated for functional verification do not correctly exercise capability mechanisms and must be filtered and post-processed to construct capabilities with appropriate bounds, permissions, and tags before they can be used as security-aware benchmarks. Security-Aware Benchmarks for Performance Exploration of CHERI