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Verification Of Risc-V Core Blocks Using Uvm

$^{1}$Asst. Prof. Nithyashree. S, $^{2}$Monisha J K, $^{2}$M G Jatin

$^{1}$Asst. Prof. Department of ECE & Dr. Ambedkar Institute of Technology

$^{2}$Students, Department of ECE & Dr. Ambedkar Institute of Technology

Abstract - The RISC-V instruction set architecture has gained significant adoption due to its open-source nature and modular design, making functional correctness and robustness of its processor cores critically important. This project focuses on the functional verification of major RISC-V processor core blocks using the Universal Verification Methodology (UVM). The verification environment is developed using System Verilog and UVM, following a reusable, scalable, and coverage-driven verification approach. Key RISC-V core blocks such as the Instruction Fetch Unit (IFU), Instruction Decode Unit (IDU), Execute Unit (ALU, MUL/DIV), Load-Store Unit (LSU), Register File, Control and Status Registers (CSR), Pipeline and Hazard Unit, and Interrupt/Exception Unit are verified individually and in integration. UVM components including sequence, sequencer, driver, monitor, scoreboard, and coverage collector are implemented to generate constrained-random instruction streams, drive transactions, and compare DUT outputs against a reference model. Functional coverage and assertion-based checks are used to ensure thorough verification of instruction execution, data integrity, pipeline behavior, and exception handling. The project demonstrates how UVM enables early bug detection, improves verification efficiency, and ensures compliance with the RISC-V specification, making the design reliable for real-world SoC integration. This work highlights industry-standard verification practices used in modern processor development.

I. INTRODUCTION

Today’s devices are highly integrated, enabling a single chip to perform many functions such as networking, wireless etc. Each function is done by an Intellectual Property (IP). Grouping all the IPs and allowing them to communicate on one chip is called System on Chip (SoC).

The increasing demand for high-performance portable SoC’s in communication and computing has added the power consumption to the traditional constraints, such as area, performance, cost, and reliability digital designs. The main agenda of this project is to verify the RISC-V processor.

II. PROBLEM STATEMENT

Modern RISC-V processor cores consist of multiple interconnected functional blocks such as instruction fetch, decode, execution, memory access, control/status registers, and exception handling units. Due to increasing architectural complexity, traditional directed test-based verification methods are insufficient to guarantee functional correctness, corner-case coverage, and protocol compliance across all instruction scenarios.

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There is a critical need for a systematic, reusable, and coverage-driven verification methodology that can validate the correct operation of individual RISC-V core blocks as well as their integrated behavior. Inadequate verification may lead to undetected functional bugs, pipeline hazards, incorrect exception handling, or non-compliance with the RISC-V specification, resulting in costly silicon re-spins.

Therefore, this project addresses the problem of verifying the functional correctness and robustness of major RISC-V core blocks by developing a UVM-based verification environment that supports constrained-random stimulus generation, automated checking, functional coverage, and scalability, ensuring reliable and standards-compliant processor design.

III. OBJECTIVES

1. Verify Key RISC-V Core Blocks Individually

• Create targeted test environments for the following blocks:
  • Instruction Fetch Unit (IFU)
  • Decode Unit
  • Execution Unit (ALU, MUL, DIV, etc.)
  • Register File
  • Control and Status Registers (CSRs)
  • Load/Store Unit (LSU)
  • Branch Prediction Unit

2. Functional Coverage and Assertions

• Define functional coverage models for each block based on RISC-V ISA specs.
• Integrate System Verilog assertions (SVA) to monitor protocol compliance and detect corner-case failures.
• Track and ensure 100% functional coverage closure.

3. Reference Model and Score boarding

• Integrate an architectural reference model (e.g., Spike or custom ISA model) for result comparison.
• Develop a scoreboard to compare expected vs actual outputs at transaction or instruction granularity.

4. Performance and Pipeline Verification

• Validate correct pipeline behaviour including forwarding, stalling, and flushing.

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• Ensure branch prediction (if implemented) functions correctly under various control flow scenarios.
• Check instruction throughput and latency metrics against design goals.

5. Documentation and Reusability

• Document all testbench components, sequences, and coverage models.
• Ensure that the verification environment is reusable across future RISC-V core revisions or SoC integrations.

IV. LITERATURE SURVEY

1. Integrated UVM-TLM Co-Simulation for RISC-V Verification (2025)

Authors: Ruizhi Qiu & Yang Liu

Core Idea: Proposes a UVM + TLM co-simulation framework for functional verification and performance evaluation of a RISC-V core. The environment models a superscalar, out-of-order RISC-V core and integrates a UVM testbench with a transaction-level TLM model. Simulation is co-driven with an external Spike ISA simulator reference model to validate functional correctness and boost simulation speed compared to cycle-accurate RTL simulation.

Relevance: Demonstrates advanced co-simulation that expands the typical UVM functional verification to include performance considerations and faster verification cycles.

2. Survey of Verification of RISC-V Processors (2025)

Authors: Chloe Tain, Savita Patil & Hussain Al-Asaad

Published in: Journal of Electronic Testing

Core Idea: A comprehensive survey covering various verification techniques for RISC-V cores, including formal, simulation-based, and hybrid approaches. The paper specifically mentions SystemVerilog and UVM verification used on an RV32I processor, splitting the verification at block and chip level and using coverage-driven constrained random testing with reference models.

Relevance: Excellent recent overview of RISC-V verification landscape, situating UVM within the broader context of verification methods.

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3. UVM Based RISC-V Verification Using Arduino Uno (2025)

Authors: Arya S. Kutwal, Pranav D. Yadav & Ajit A. Ware

Journal: IJRASET

Core Idea: Builds a UVM environment for a RISC-V processor core, adding an unusual twist by integrating with an Arduino Uno for real-time visualization. It demonstrates constrained-random tests, coverage collection, assertion verification, and over 90% functional coverage on basic instruction flows.

Relevance: Shows practical application of UVM for processor verification and aids instructional understanding, though non-standard results visualization.

4. UVM Verification of RISC-V Instruction Set (2024)

Authors: Paldurai K. et al.

Conference: ICSSEECC 2024

Core Idea: Presents a UVM methodology dedicated to verifying RISC-V instruction set execution. The environment includes UVM testbench components (agents, scoreboard, coverage), and highlights stimuli generation, instruction monitoring, and comprehensive simulation reporting.

Relevance: Provides a focused case on instruction-level UVM verification, critical for validating ISA compliance.

5. RISC-V UVM Verification Thesis (2024)

Institution: Politecnico di Milano

Core Idea: Academic thesis describing a full UVM infrastructure for RISC-V verification, integrating Spike as a reference ISA model, random instruction generators, directed tests, and coverage collection. Emphasizes reuse, open-source toolchain and the benefits of UVM testbench design.

Relevance: Useful methodology example showing how UVM components are organized and tools integrated for RISC-V.

6. System-Level Verification of Multi-Core RISC-V (2025)

Authors: Palomar, Genovese et al.

Event: RISC-V Summit Europe 2025

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Core Idea: Verification strategy for a multi-core RISC-V system, reusing core-level UVM environments at system level. Uses Spike ISS as a reference model, RISCV-DV for random binaries, directed tests and an assertions suite to improve coverage.

Relevance: Shows scalable UVM verification from core to system and use of reference models in complex multi-core verification.

7. CORE-V-VERIF – UVM Environment for RISC-V (2020+)

Organization: OpenHW Group / Tessolve

Contribution: CORE-V-VERIF is an open-source SV/UVM environment used to verify RISC-V cores like the CV32E40P. It includes ISA stimulus generators, bus agents, assertions and coverage models.

Relevance: Foundation for many current UVM verification flows used in industry and academia, showing long-term ecosystem support.

V. METHODOLOGY

• VERIFICATION OF KEY RISC-V CORE BLOCKS USING UVM” follows a structured verification flow based on the Universal Verification Methodology (UVM) to validate the functionality of key blocks in a RISC-V processor core. This includes understanding the design under test (DUT), creating a UVM testbench, developing test scenarios, executing simulations, and analysing results.

1. Study and Understand the DUT (Design Under Test)

• Identify and select key RISC-V core blocks for verification (e.g., ALU, Register File, Decoder, Control Unit).
• Understand the functionality, input-output interfaces, and design specifications of each block.
• Review the RTL implementation (written in System Verilog).

2. Set Up the UVM Verification Environment

• Create a UVM-based test bench comprising:
  • UVM Test: Top-level configuration and control.
  • Environment : Contains agents, scoreboards, and monitors.
  • Agent: Composed of driver, sequencer, and monitor.
  • Sequence & Sequence Item: Generate stimulus for the DUT.

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• Driver: Converts sequence items into pin-level transactions.
• Monitor: Observes DUT output and sends data to scoreboard or coverage collectors.
• Scoreboard: Compares expected output with actual output (checking functionality).

3. Test bench Integration with DUT

• Instantiate the DUT within a test bench wrapper.
• Connect DUT ports to driver and monitor interfaces using virtual interfaces.
• Map sequence items to DUT signals.

4. Develop and Run Test Cases

• Create directed and constrained-random test sequences.
• Target functional scenarios (e.g., ALU operations like ADD, SUB, AND, OR; Register read/write operations).
• Use assertions and checkers to validate expected outputs.

5. Functional Coverage and Assertions

• Define coverage points (e.g., instruction types, ALU operations).
• Implement cover groups in the monitor to track exercised scenarios.
• Add System Verilog assertions (SVA) to check protocol or control logic correctness.

6. Simulation and Debugging

• Compile and simulate the design using a simulator (e.g., ModelSim, Questa, VCS).
• Analyze waveform and log files to debug failures.
• Use UVM reporting mechanisms (uvm_info, uvm_error) to track test bench

7. Coverage Analysis and Regression

• Measure code coverage and functional coverage.
• Perform regression testing to ensure repeated correctness across multiple runs.
• Optimize test cases to close coverage gaps.

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8. Documentation and Reporting

• Document the verification environment, test scenarios, coverage results, and bugs found.
• Summarize conclusions and suggest improvements for design or verification methodology.
• Activity.

VI. OPERATIONAL LOGIC

• DUT Initialization

The RISC-V core is instantiated as DUT and initialized using clock and reset to a known state.

• Instruction Generation

UVM sequences generate constrained-random RISC-V instructions covering all formats and corner cases.

• Stimulus Driving

The driver converts sequence items into signal-level transactions and applies them to the DUT.

• Core Execution

The DUT executes instructions through IFU, IDU, ALU/LSU, CSR, pipeline, and exception units.

• Monitoring

Monitors capture instruction flow, register updates, memory access, and exception events.

• Reference Comparison

The scoreboard compares DUT results with a reference model based on the RISC-V ISA.

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• Assertion Checking

Assertions verify protocol rules, pipeline order, CSR access, and exception behavior.

• Functional Coverage

Coverage collectors track instruction execution, operand combinations, and corner scenarios.

• Debug Iteration

Failures and coverage gaps are analyzed, and constraints are refined to improve coverage.

• Coverage Closure

Verification ends after achieving coverage goals and generating final reports.

Software Specifications

Verilog is a Hardware Description Language (HDL) used to model and simulate digital electronic systems such as processors, memory, and other digital logic. It allows designers to describe the behaviour and structure of electronic circuits in a textual form, enabling simulation, verification, and synthesis into actual hardware.

1. Programming and Verification Language

• System Verilog

Used for writing both the RTL design (if required) and the UVM-based verification testbench.

• UVM (Universal Verification Methodology)

A System Verilog-based methodology used to create modular, reusable test benches.

2. Simulator

• ModelSim / QuestaSim (Mentor Graphics)

Industry-standard simulator with System Verilog and UVM support.

3. UVM Library

• UVM Version: IEEE 1800.2 (UVM 1.2 or UVM 1.1d).

4. Code Editor

• Code editor:

• Visual Studio Code (recommended, with extensions for System Verilog).

• Simulator's built-in editor (Questa Sim IDE).

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5. Waveform Viewer

• Built into the simulator (Questa Sim Waveform Viewer).

VII. RESULTS

The project successfully developed a UVM-based verification environment for major RISC-V core blocks, enabling systematic and coverage-driven functional verification. All targeted units—including IFU, IDU, Execute Unit, LSU, Register File, CSR, Pipeline, and Exception Unit—were verified against the RISC-V specification using constrained-random testing, assertions, and a reference model.

Functional and assertion coverage goals were achieved, critical corner-case bugs were identified and resolved, and the verification framework proved to be scalable, reusable, and effective, ensuring a reliable and standards-compliant RISC-V processor design suitable for SoC integration.

VIII. CONCLUSIONS

In verification of key RISC-V Core Blocks using UVM, we will demonstrate the application of the Universal Verification Methodology (UVM) in verifying critical components of a RISC-V processor core. Through the development of a structured and reusable UVM-based test bench, key blocks such as the ALU, Register File, and Control Unit will be thoroughly tested against their expected functional behaviour.

ACKNOWLEDGEMENT

The author thank the Department of Electronics and Communication Engineering, Dr. AIT Bangalore, for guidance and support in completing this project.

REFERENCES

1. RISC-V Foundation, The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.2, 2019.
2. IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language, IEEE Std 1800-2023.
3. Accellera Systems Initiative, Universal Verification Methodology (UVM) 1.2 User's Guide, 2015.
4. Accellera Systems Initiative, UVM Class Reference, 2020.
5. Waterman, A., Lee, Y., Patterson, D., & Asanović, K., “The RISC-V Instruction Set Architecture,” Proceedings of the 2011 20th IEEE Symposium on Computer Arithmetic, IEEE, pp. 1-5.

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6. C. E. LaForest, “Understanding RISC-V,” IEEE Potentials, vol. 38, no. 1, 2019, pp. 16–23.
7. Kaushik, P. & Garg, S., “Design and Verification of RISC-V Based Processor Using UVM,” International Journal of Engineering Research & Technology (IJERT), vol. 9, issue 7, 2020.
8. Mohanty, S. & Chattopadhyay, S., “An Efficient Verification Environment for RISC-V CPU Using UVM,” 2021 International Conference on VLSI Design and Test (VDAT), IEEE, 2021.
9. Lee, D., & Kim, Y., “UVM-Based Verification Methodology for Pipelined Processors,” Microelectronics Journal, vol. 76, pp. 78–89, 2018.
10. Mentor Graphics QuestaSim User Manual, Siemens EDA, 2022.

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