AI Planning Algorithm Synthesis

Concept

AI Planning Algorithm Synthesis is a test generation methodology that uses automated planning algorithms to synthesize verification stimulus for complex designs. In the RISC-V verification context, Breker Verification Systems positions this approach as an alternative or complement to Constrained Random Verification for tackling core and SoC verification challenges.

First seen 7/6/2026

Last seen 7/6/2026

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AI Planning Algorithm Synthesis

Overview

AI Planning Algorithm Synthesis is an automated test generation methodology in which AI-based planning algorithms are used to synthesize stimulus for functional verification. Rather than relying solely on random or constrained-random stimulus, planning algorithms construct test sequences that exercise specific scenarios, coverage targets, or system-level behaviors in a directed fashion.

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RELATIONSHIPS

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Breker Verification Systems ← implements 90% 1e

The presentation compares Constrained Random Verification against AI Planning Algorithm Synthesis, with Breker employing the latter.

Constrained Random Verification compares with → 97% 1e

The slide explicitly contrasts AI Planning Algorithm Synthesis with Constrained Random Verification as competing test generation approaches.

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Breker Verification Systems IMPLEMENTS Extracted graph relationship

Constrained Random Verification COMPARES_WITH Extracted graph relationship

CITATIONS

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[1] Automated test generation is a key requirement to meet quality expectations for RISC-V verification. RISC-V Core & SoC Verification: A New Normal in Verification Techniques

[2] RISC-V verification challenges include custom instruction verification, compliance assurance, and a broad range of architectures from embedded cores to application processors. RISC-V Core & SoC Verification: A New Normal in Verification Techniques

[3] AI Planning Algorithm Synthesis is explicitly compared with Constrained Random Verification as a stimulus generation approach. RISC-V Core & SoC Verification: A New Normal in Verification Techniques

[4] Breker Verification Systems provides Test Suite Synthesis for RISC-V cores and SoCs, applying automated tests based on prior x86 and Arm verification experience. RISC-V Core & SoC Verification: A New Normal in Verification Techniques

[5] The synthesized test plans support concurrent test execution across RISC-V core verification components. RISC-V Core & SoC Verification: A New Normal in Verification Techniques