Skip to content
STIMSMITH

AI Planning Algorithm Synthesis

Concept WIKI v1 · 7/6/2026

AI Planning Algorithm Synthesis is a test generation methodology that uses automated planning algorithms to synthesize verification stimulus for complex designs. In the RISC-V verification context, Breker Verification Systems positions this approach as an alternative or complement to Constrained Random Verification for tackling core and SoC verification challenges.

AI Planning Algorithm Synthesis

Overview

AI Planning Algorithm Synthesis is an automated test generation methodology in which AI-based planning algorithms are used to synthesize stimulus for functional verification. Rather than relying solely on random or constrained-random stimulus, planning algorithms construct test sequences that exercise specific scenarios, coverage targets, or system-level behaviors in a directed fashion.

Application to RISC-V Verification

In the context of RISC-V core and SoC verification, Breker Verification Systems describes automated test generation as a key requirement for meeting the quality expectations established by established processor ecosystems. The presentation highlights that organizations such as Arm spend approximately $150M per year on roughly 10¹⁵ verification cycles per core, establishing a quality bar that is difficult for RISC-V development groups to meet without significant automation and reuse.

The methodology is positioned as part of a broader verification stack that addresses RISC-V-specific needs including custom instruction verification, compliance assurance, and the wide architectural spread from embedded cores to application processors. Automation, reuse, and "new thinking" are identified as necessary to overcome these verification challenges.

Comparison With Constrained Random Verification

The presentation explicitly contrasts AI Planning Algorithm Synthesis with Constrained Random Verification. The two approaches are presented as alternative or complementary stimulus generation strategies used to populate the verification environment.

Cross-Component Capability

AI Planning Algorithm Synthesis, as implemented through Breker's Test Suite Synthesis approach, is applied across RISC-V core verification components, enabling coordinated test generation that crosses structural verification boundaries rather than generating stimulus for a single component in isolation.

Concurrent Test Execution

The synthesized test plans support concurrent test execution, allowing multiple scenarios to run in parallel to increase effective verification throughput.

Notes

  • Detailed technical mechanics of the AI planning algorithms (e.g., the specific planning formalism, solver, or cost model) are not described in the available evidence.
  • The RISC-V International certification committee's role is mentioned for architectural compliance testing, but the specific interaction between AI Planning Algorithm Synthesis and certification is not detailed in the evidence.

LINKED ENTITIES

2 links
Breker Verification Systems IMPLEMENTS
Constrained Random Verification COMPARES_WITH

CITATIONS

5 sources
5 citations
[1] Automated test generation is a key requirement to meet quality expectations for RISC-V verification. RISC-V Core & SoC Verification: A New Normal in Verification Techniques
[2] RISC-V verification challenges include custom instruction verification, compliance assurance, and a broad range of architectures from embedded cores to application processors. RISC-V Core & SoC Verification: A New Normal in Verification Techniques
[3] AI Planning Algorithm Synthesis is explicitly compared with Constrained Random Verification as a stimulus generation approach. RISC-V Core & SoC Verification: A New Normal in Verification Techniques
[4] Breker Verification Systems provides Test Suite Synthesis for RISC-V cores and SoCs, applying automated tests based on prior x86 and Arm verification experience. RISC-V Core & SoC Verification: A New Normal in Verification Techniques
[5] The synthesized test plans support concurrent test execution across RISC-V core verification components. RISC-V Core & SoC Verification: A New Normal in Verification Techniques