2026-07-05
3 items 82 entities 144 connections
Processed 45 entities and 91 relations.
SNAP AFL Coverage-Guided Fuzzing Coverage Tracing Hardware-Assisted Fuzzing Source Code Instrumentation Dynamic Binary Instrumentation Intel Processor Trace Coverage Bitmap Edge Coverage CPU Pipeline Speculative Execution Branch Prediction Bitmap Update Queue Last Branch Queue RISC-V BOOM RISC-V Control Flow Tracing Data Flow Analysis Binary Rewriting RetroWrite QEMU Micro-architectural State Basic Block Hardware Primitives FPGA Taint Analysis Control and Status Registers Memory Request Aggregation Opportunistic Bitmap Update Binutils PHMon Hardware Support to Improve Fuzzing Performance and Precision Ren Ding Yonghae Kim Fan Sang Wen Xu Gururaj Saileshwar Taesoo Kim Georgia Institute of Technology Trace Decision Logic Edge Encoding Out-of-Order Execution Synopsys Design Compiler SPEC CPU2006
Processed 2 entities and 1 relations.
Processed 35 entities and 52 relations.
LLM4DV Test Stimuli Generation Constrained-Random Testing Design Verification Functional Coverage Coverage Plan Coverage Bin LLM4DV Framework Coverage-Feedback Prompting Template Missed-Bin Sampling Best-Iterative-Message Sampling Dialogue Restarting Design-Under-Test Primitive Data Prefetcher Core Ibex Instruction Decoder Ibex CPU RISC-V GPT-3.5-turbo-0613 Llama 2 7B Verilator cocotb Assertion-Based Verification Concolic Testing Large Language Model RTL Zixi Zhang Greg Chadwick Hugo McNally Yiren Zhao Robert Mullins University of Cambridge lowRISC Imperial College London Coverpoint Type-based Sampling Mixed Coverpoint Type-based and Pure Random Sampling