lowRISC

Organization

lowRISC is a not-for-profit engineering company that creates and maintains commercial-grade open-source silicon designs through a collaborative Silicon Commons approach. It maintains Ibex, a production-quality open-source 32-bit RISC-V CPU core used in contexts such as OpenTitan.

First seen 5/27/2026

Last seen 6/9/2026

Evidence 7 chunks

Wiki v1

WIKI

lowRISC

lowRISC is a not-for-profit engineering company that creates and maintains commercial-grade open-source silicon designs through its collaborative Silicon Commons approach.

Maintained silicon designs

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NEIGHBORHOOD

2 nodes · 1 edges

graph · lowRISC · depth=1

RELATIONSHIPS

3 connections

OpenTitan ← published by 100% 1e

OpenTitan is published by lowRISC and Google.

Ibex ← published by 1e

Ibex is published and maintained by lowRISC on GitHub.

TestRIG uses → 90% 1e

lowRISC is among the organizations using and contributing to TestRIG.

CITATIONS

9 sources

9 citations — click to expand

[1] lowRISC is a not-for-profit engineering company that creates and maintains commercial-grade open-source silicon designs through a collaborative Silicon Commons approach. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[2] lowRISC maintains Ibex, a production-quality open-source 32-bit RISC-V CPU core written in SystemVerilog. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[3] Ibex is heavily parameterizable, suited for embedded control applications, has undergone extensive verification, and has seen multiple tape-outs. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[4] Ibex supports the RISC-V I or E, M, C, and B/Bit Manipulation extensions. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[5] Ibex is used in OpenTitan, an open-source silicon Root of Trust project described as a secure chip providing trustworthy functions for strong device or system security. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[6] Ibex is verified using a UVM-based testbench with co-simulation against the Spike ISS reference model and binaries generated from RISC-DV random-instruction-generator output. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[7] The Ibex testbench provides randomized memory timings, memory errors, interrupts, and debug requests, and implements a comprehensive test plan and coverage plan. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[8] Ibex verification closure targets supported configurations, with current effort focused on the OpenTitan configuration, which has nightly regression runs. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[9] The cited source reports 90% code and functional coverage, more than 90% regression pass rate, and fully implemented but not yet closed test and coverage plans for Ibex verification maturity tracking. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi