2026-07-04
5 items 154 entities 169 connections
Processed 42 entities and 49 relations.
MicroTESK Test Program Generation Architecture Description Language Instruction Set Model Test Knowledge Test Templates Constraint Satisfaction Problem Functional Verification Model-Based Testing Reconfigurable Test Program Generator Genesys-Pro RAVEN Z3 Solver SMT-LIB nML Sim-nML Test Template Description Language Coverage Model Graph-Based Functional Test Generation SAT-Based Bounded Model Checking Cache Memory Modeling Configuration Files MIPS Instruction Set Architecture Microprocessor Architecture Model EXPRESSION ADL Ruby Scripting Language Alexander Kamkin Andrei Tatarnikov Prabhat Mishra Nikil Dutt Heon-Mo Koo Institute for System Programming of RAS IBM Research Lab Obsidian Software Inc. Microsoft Research MicroTESK: An ADL-Based Reconfigurable Test Program Generator for Microprocessors Reconfigurable Model-Based Test Program Generator for Microprocessors Graph-Based Functional Test Program Generation for Pipelined Processors Functional Test Generation using SAT-based Bounded Model Checking SMT-Based Test Program Generation for Cache-Memory Testing Memory Management Unit Pipeline Control Unit
Processed 5 entities and 2 relations.
Processed 30 entities and 41 relations.
ReFuzz: Reusing Tests for Processor Fuzzing with Contextual Bandits Fuzzilicon: A Post-Silicon Microcode-Guided x86 CPU Fuzzer GoldenFuzz: Generative Golden Reference Hardware Fuzzing ReFuzz Fuzzilicon GoldenFuzz processor fuzzing contextual bandits test mutation post-silicon fuzzing microcode-level instrumentation coverage-guided fuzzing golden-reference model fuzzing microarchitectural vulnerability detection hardware security x86 CPU RISC-V microcode Chen Chen Zaiyan Xu Mohamadreza Rostami David Liu Dileep Kalathil Ahmad-Reza Sadeghi Jeyavijayan Rajendran Johannes Lenzen Lichao Wu Huimin Li Nikhilesh Singh NDSS 2026
Processed 67 entities and 69 relations.
Condominium BlackParrot FPGA emulation RTL simulation coverage-guided fuzzing high-fidelity coverage metric ISA cosimulation cycle-accurate performance profiling latency-aligned group-coverage CAM-based Group Coverage Engine (CCE) automated coverage instrumentation formal verification clock-gating mechanism architectural checkpointing random constrained testing ISA compliance testing coverage-guided hardware fuzzing FPGA-accelerated coverage collection test stimulus generation sliding-window EXP3 multi-armed bandit bug injection black-box fuzzing PC generation instruction cache branch prediction cache coherence performance counters system-call abstraction heterogeneous prototyping cluster Zynq-based architecture Verilator RISC-V ISA scale-down prototyping AXI interface DPI-C interface PL-Shell functional verification continuous integration Linux boot BaseJump STL synthesized hardware probes FPGA bitstream generation Farzam Gilani Michael Taylor Mark Oskin Daniel Petrisko Anoop Mysore Nataraja Bespoke Silicon Group University of Washington covergroup coverpoint RTL datapath benchmark suite SPEC benchmark CoreMark instructions-per-clock (IPC) pipeline stall attribution non-intrusive emulation progressive coverage BRAM-based coverage engine one-to-one coverage mapping PYNQ API Vivado GDB Bedrock coherence protocol virtual-to-physical address translation catch-up ALU
Processed 10 entities and 8 relations.