Automated Coverage Instrumentation

Concept

Automated coverage instrumentation is the automated identification and tagging of coverage points in a hardware design, implemented in ZP Cosim as Section 3.1 of the ZP Cosim chapter. It automates insertion of Mux Toggle Coverage (and a proof-of-concept case-statement coverage) coverpoints into a design's top-level wrapper using a Surelog/UHDM-based parse-and-walk pipeline, enabling coverage collection during both simulation and FPGA emulation of the Processor-Under-Test.

First seen 7/4/2026

Last seen 7/11/2026

Evidence 6 chunks

Wiki v2

WIKI

Automated Coverage Instrumentation

Overview

Automated coverage instrumentation is the step, introduced in ZP Cosim, that automatically identifies and tags the design elements whose states need to be monitored during simulation or emulation in order to infer the coverage effected by test programs. It is presented as Section 3.1, "Automated Coverage Instrumentation," of the ZP Cosim chapter, with subsections covering Implementation (3.1.1), Surelog (3.1.2), Universal Hardware Data Model (3.1.3), Coverage Walker (3.1.4), Implementation of Mux Toggle Coverage Metric (3.1.5), and subsequent coverspace-processing subsections (3.1.6–3.1.11).

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

2 connections

coverage-guided hardware fuzzing ← uses 90% 2e

Coverage-guided hardware fuzzing uses automated coverage instrumentation

ZP Cosim ← introduces 98% 2e

ZP Cosim introduces a novel implementation of automated coverage instrumentation

LINKED ENTITIES

1 links

ZP Cosim INTRODUCES Extracted graph relationship

CITATIONS

13 sources

13 citations — click to expand

[1] Automated coverage instrumentation is presented as Section 3.1 of the ZP Cosim chapter, with subsections 3.1.1 Implementation, 3.1.2 Surelog, 3.1.3 Universal Hardware Data Model, 3.1.4 Coverage Walker, 3.1.5 Implementation of Mux Toggle Coverage Metric, and 3.1.6–3.1.11 coverspace processing. ©Copyright 2023 Anoop Mysore Nataraja

[2] ZP Cosim introduces a new automated coverage collection implementation built on existing open-source offerings, motivated by the requirement of identifying key design elements whose states need to be monitored during simulation or emulation for inferring the coverage effected by test programs. ©Copyright 2023 Anoop Mysore Nataraja

[3] Design elements that may be monitored include structural elements (expressions in assignment statements, case statements, assertions, etc.) and functional elements (complex composite expressions corresponding to specific functionalities of the hardware). ©Copyright 2023 Anoop Mysore Nataraja

[4] ZP Cosim demonstrates and implements automated Mux Toggle Coverage popularized by Kevin Laeufer et al. [81], together with a proof-of-concept case-statement coverage. ©Copyright 2023 Anoop Mysore Nataraja

[5] Mux Toggle Coverage treats muxes as sources of multiplicity in hardware states; the cumulative combination of toggles in mux-selects across all muxes amounts to all different possible control paths, and the cross-product of toggles on (interacting) muxes is a truer indication of coverage than individual toggles. ©Copyright 2023 Anoop Mysore Nataraja

[6] Case-statement coverage is a structural/code coverage metric that assesses the completeness of a test vector in exercising all the case-statement control paths and is not a standalone metric. ©Copyright 2023 Anoop Mysore Nataraja

[7] The implementation packages a parameterized, modifiable walker that parses the hardware design description and outputs hierarchically referenced full-pathnames of mux select-signals, using Surelog [37], UHDM [38], and a customizable walker. ©Copyright 2023 Anoop Mysore Nataraja

[8] A coverpoint is a boolean or multi-bit expression (wire or register) in the HDL that is assessed, usually for toggles, for determining the coverage of a test case on the hardware in question. ©Copyright 2023 Anoop Mysore Nataraja

[9] Generated coverpoints are assembled into the top-level wrapper via SystemVerilog assertions for simulations, or via dedicated coverage collection modules with memory modules and read interfaces for emulations/post-processing. ©Copyright 2023 Anoop Mysore Nataraja

[10] ZP Cosim provides GNU Make routines to automatically package the identified hierarchically referenced coverpoints by grouping and wiring them into coverage modules in the top-level wrapper of the design under consideration. ©Copyright 2023 Anoop Mysore Nataraja

[11] Surelog [37] is a SystemVerilog 2017 [13] pre-processor, parser, elaborator, and UHDM compiler providing IEEE Design/TB C/C++ VPI [40] and Python AST APIs; ZP Cosim uses Surelog to take a file list of distributed SystemVerilog design files plus parameters (top-module, library extensions, compilation ordering, parameter overrides, full/folded UHDM elaboration) and generate a walkable UHDM object. ©Copyright 2023 Anoop Mysore Nataraja

[12] The ZP Cosim control loop runs on the Processing Subsystem (host processor close to the FPGA): it loads test programs onto the PUT and a Dromajo golden-reference ISA simulator, iteratively steps the execution trace, performs cosimulation/analysis, extracts and processes coverage from the PUT upon program termination, derives mutations, and runs program-generation or benchmark step-through. ©Copyright 2023 Anoop Mysore Nataraja

[13] ZP Cosim builds on the existing Zynq-Parrot infrastructure [9] that enables rapid FPGA prototyping for BlackParrot processor on Zynq 7000 and Ultrascale FPGA devices. ©Copyright 2023 Anoop Mysore Nataraja