Cache Memory Modeling

Concept

Cache Memory Modeling refers to the formal description of processor cache structures and their behavior for the purpose of functional verification and test program generation. It captures buffer configuration attributes and represents cache events (hits, misses) as constraint satisfaction problems (CSPs), enabling automated test data generation through SMT solvers such as Z3.

First seen 7/4/2026

Last seen 7/4/2026

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Wiki v1

WIKI

Overview

Cache Memory Modeling is the activity of formally describing the structure and behavioral characteristics of processor caches so that they can be reasoned about and exercised by automated test-generation tools. In the context of microprocessor verification, the model must capture both the static configuration of cache buffers and the dynamic conditions under which cache events (hits, misses, evictions) occur, including dependencies on prior instructions.

Buffer Configuration Attributes

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RELATIONSHIPS

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MicroTESK ← uses 90% 1e

MicroTESK uses cache memory modeling through configuration files to specify buffer structures.

SMT-Based Test Program Generation for Cache-Memory Testing ← introduces 90% 1e

This paper introduces SMT-based approaches for cache memory testing.

LINKED ENTITIES

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MicroTESK USES Extracted graph relationship

SMT-Based Test Program Generation for Cache-Memory Testing INTRODUCES Extracted graph relationship

CITATIONS

7 sources

7 citations — click to expand

[1] Buffer configuration information includes set size (associativity), number of sets, line field description, address-to-index translation rule, rule for checking if a line and an address match, and data displacement policy. MicroTESK: An ADL-Based Reconfigurable Test Program Generator for Microprocessors

[2] Hit and miss situations in a cache buffer can be formulated as CSPs over the address being used to access data and the state of the buffer. MicroTESK: An ADL-Based Reconfigurable Test Program Generator for Microprocessors

[3] Instruction dependencies are part of Test Knowledge extracted from Configuration Facilities and affect cache modeling because instructions modify the state accessed by subsequent instructions. MicroTESK: An ADL-Based Reconfigurable Test Program Generator for Microprocessors

[4] TTDL allows test situations involving cache events to be expressed, e.g., `hit([L1(), L2()], [25, 50, 75])`, which specifies target caches and the probability of a hit event occurrence. MicroTESK: An ADL-Based Reconfigurable Test Program Generator for Microprocessors

[5] MicroTESK uses the SMT-LIB language to formulate CSPs and uses the Z3 SMT solver from Microsoft Research to solve them, with bit-vector support suited to modeling registers, cache, and main memory. MicroTESK: An ADL-Based Reconfigurable Test Program Generator for Microprocessors

[6] The SMT-Based Test Program Generation for Cache-Memory Testing approach was introduced by E. Kornykhin at the East-West Design & Test Symposium (EWDTS) in 2009. MicroTESK: An ADL-Based Reconfigurable Test Program Generator for Microprocessors

[7] MicroTESK uses the nML/Sim-nML ADL formalism to describe target microprocessor designs, including their caches, and extracts Test Knowledge from ADL specifications. MicroTESK: An ADL-Based Reconfigurable Test Program Generator for Microprocessors