2026-07-03
6 items 291 entities 331 connections
Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V - CARRV at ISCA 2022
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Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V S Pawan Kumar Shrreya Singh Neel Gala Allen Baum InCore Semiconductors IIT Gandhinagar Esperanto Technologies Architectural Testing RISC-V ISA Coverage Specification Signature-Based Testing Design Verification Coverpoint Data Propagation Analysis Constraint Satisfaction Problem Min-Conflict Solver Backtracking Solver SMT Solver-Based Test Generation Mutation-Based Test Generation Negative Testing Directed Test Generation RISCV-ISAC RISCV-CTG CGF Format RTL UVM Test Format Specification RISC-V Architectural Test Suite Directed Test Generation
Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors
source →Processed 37 entities and 47 relations.
Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors Heon-Mo Koo Prabhat Mishra Intel Corporation University of Florida Directed Test Generation Random Test Generation Biased-Random Test Generation FSM Coverage-Directed Test Generation Test Compaction Dynamic Test Compaction Static Test Compaction Finite State Machine (FSM) Model FSM State Coverage FSM Transition Coverage Pipeline Interaction Coverage Functional Coverage Unreachable State Identification Illegal State Transition Identification Redundant State and Transition Elimination Inevitable State Model Checking for Test Generation Architecture Description Language (ADL) Temporal Logic Property Counterexample-based Test Generation RTL Implementation Simulation-based Validation Functional Fault Set Covering Fault Simulation Genesys-Pro MIPS Processor Model (FSM) e500 Processor Model (FSM) Pipelined Processor Functional Validation ISA-level Test Program Generation Path Selection in FSM Regression Testing
Processed 49 entities and 39 relations.
Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study Heon-Mo Koo Prabhat Mishra Jayanta Bhadra Magdy Abadir University of Florida Freescale Semiconductor Inc. micro-architectural test generation directed test generation simulation-based validation instruction set architecture (ISA) random test generation biased-random test generation pipeline interaction fault temporal logic properties decompositional model checking counterexample generation processor model decomposition Linear Temporal Logic (LTL) finite state machine (FSM) model state-space explosion pipeline graph coverage functional fault model data forwarding register renaming out-of-order execution dynamic scheduling dynamic speculation superscalar processor reservation station reorder buffer completion queue clock-based counterexample integration test compaction RTL simulation SAT-based bounded model checking micro-architectural fault temporal specification language pipelined processor model Cadence SMV model checker Power Architecture Technology e500 processor MIPS processor deeply pipelined architecture property decomposition graph-based functional test program generation FSM model partitioning instruction-level parallelism
Processed 58 entities and 72 relations.
HARTBREAKER determinism anchors control-flow anchors data-flow anchors synchronization anchors differential testing pre-silicon fuzzing litmus tests non-determinism control-flow non-determinism data-flow non-determinism RVWMO memory consistency model inter-processor interrupts program-level determinism Preserved Program Order rules multi-hart CPU instruction set simulator RTL simulation CLINT store buffer Sequential Consistency Coherence of Read-Read microarchitectural state space exploration instruction throughput Cascade RISCV-DV DifuzzRTL TestRIG ProcessorFuzz INSTILLER TheHuzz MorFuzz RISCVuzz Spike Verilator UVM Rocket BOOM Toooba NaxRiscv XiangShan Quentin Bordier Tobias Kovats Flavien Solt Kaveh Razavi ETH Zurich UC Berkeley RISC-V MCM solver landing zone load value axiom syntactic dependency speculative execution out-of-order execution mret instruction MIP register HARTBREAKER paper
Processed 89 entities and 106 relations.
Instruction Set Architecture CPU Verification Binary Analysis Binary Lifting ISA Semantics ISA Specification Processor Description Language Instruction Encoding Instruction Decoding Microarchitecture Simulation Instruction Set Simulator Formal Verification of Processors Memory Consistency Model Peephole Superoptimization Disassembly Code Generation Abstract Interpretation Instruction-Level Abstraction Axiomatic Concurrency Model Microcode Verification Reverse Engineering of Instruction Encodings System-on-Chip Verification Capability Architecture RTL Verification Hypervisor Verification Instruction Set Processor (ISP) Description Binary Translation Test Oracle Spectre/Microarchitectural Side Channel Sail ISA Specification Language Arm Architecture Specification Language (ASL) L3 Specification Language LISA Machine Description Language SLED (Specification Language for Encoding and Decoding) nML QEMU TCG (Tiny Code Generator) Intermediate Representation BAP (Binary Analysis Platform) BinRec Binary Lifter McSema Binary Lifter Remill Binary Lifting Library Capstone Disassembler Zydis x86 Decoder/Disassembler Library Dagger Binary Lifter LLVM-MCtoLL Binary Lifter reopt Binary Lifter rev.ng Reverse Engineering Tool Isla ISA Semantics Tool x86isa ISA Model (ACL2) UCLID5 TSL (Transfer Specification Language) Pydgin Instruction Set Simulator Generator ZSim Architectural Simulator HOIST Static Analyzer Derivation System ISA-Formal New Jersey Machine-Code Toolkit RockSalt SFI Tool Vale Cryptographic Assembly Verifier Examiner ARM Emulator Consistency Checker ARM Architecture RISC-V Architecture x86/x86-64 Architecture POWER Architecture CHERI Capability Architecture ISA Semantics for ARMv8-A, RISC-V, and CHERI-MIPS (armstrong:popl19:2019) Detailed Models of ISAs: From Pseudocode to Formal Semantics (armstrong:arw:2018) Isla: Integrating Full-Scale ISA Semantics and Axiomatic Concurrency Models (armstrong:cav:2021) A Complete Formal Semantics of x86-64 User-Level ISA (dasgupta:pldi) End-to-End Verification of ARM Processors with ISA-Formal (reid:cav:2016) Trustworthy Specifications of ARM v8-A and v8-M System Level Architecture (reid:fmcad:2016) Who Guards the Guards? Formal Validation of the ARM v8-M Architecture Specification (reid:oopsla:2017) Automatic Generation and Validation of Instruction Encoders and Decoders (xu:cav:2021) Automated Synthesis of Symbolic Instruction Encodings from I/O Samples (godefroid:pldi:2012) Synthesizing Formal Models of Hardware from RTL for Efficient Verification of Memory Model Implementations (hsiao:micro:2021) Instruction-Level Abstraction (ILA): A Uniform Specification for SoC Verification (huang:todaes:2019) Modelling the ARMv8 Architecture Operationally: Concurrency and ISA (flur:popl:2016) Simplifying ARM Concurrency: Multicopy-Atomic Axiomatic and Operational Models for ARMv8 (pulte:popl:2017) Solver Aided Reverse Engineering of Architectural Features (zorn:iscawddd:2017) Reverse-Engineering Instruction Encodings (hsieh:usenix:2001) Executable ISA Model Pseudocode-to-Formal-Semantics Translation Symbolic Execution for ISA Testing Retargetable Code Generation Meta-Tracing JIT Compilation for ISS Axiomatic Hardware-Software Contracts Machine Code Decompilation Abstract Transfer Function Derivation Separation Logic for Machine Code Instruction Fuzzing / Differential Testing
Processed 28 entities and 23 relations.
MA2TG Automatic Test Program Generation Constraint Satisfaction-based Test Generation Random Test Program Generation Architecture Description Language Functional Verification Microprocessor Architecture Modeling Specification-driven Test Generation User Constraints File DLX Processor MA2TG: A Functional Test Program Generator for Microprocessor Verification Tun Li Danni Zhu Yang Guo Gongjie Liu Sikun Li National University of Defense Technology AVPGEN EXPRESSION BNF-based Test Program Generation Graph-based Functional Test Program Generation Pipelined Processor Verification Prabhat Mishra Nikil Dutt Eyal Bin Avi Ziv Aharon Aharon PowerPC Processor Verification