CLINT (Core Local Interruptor)

Concept

The Core Local Interruptor (CLINT) is the default interrupt controller standardized for RISC-V. It provides memory-mapped registers used to deliver software-generated interrupts—including inter-processor interrupts (IPIs)—to a hart by setting the MSIP bit in the hart's mip CSR. The CLINT has been criticized for lacking configurability in prioritization and preemption, motivating the more capable CLIC extension.

First seen 7/3/2026

Last seen 7/3/2026

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CLINT (Core Local Interruptor)

The Core Local Interruptor (CLINT) is the default interrupt controller standardized by the RISC-V architecture. It exposes a small set of memory-mapped registers that software uses to raise interrupts on a hart, including the timer interrupt and software-generated (inter-processor) interrupts.

Role in the RISC-V Interrupt Architecture

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RISC-V part of → 100% 1e

CLINT is the RISC-V-specified Core Local INTerrupt controller.

NaxRiscv part of → 90% 1e

NaxRiscv has a CLINT implementation with a bug discovered by HARTBREAKER.

inter-processor interrupts ← uses 100% 1e

IPIs are sent through the CLINT peripheral.

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CITATIONS

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6 citations — click to expand

[1] The Core Local Interruptor (CLINT) is the default interrupt controller standardized by RISC-V. HARTBREAKER: Deterministic Fuzzing of Multi-Hart RISC-V CPUs

[2] IPIs are generally sent through a memory-mapped peripheral, usually the RISC-V-specified Core Local INTerrupt controller (CLINT), by setting the MSIP bit of the mip CSR of the target hart. HARTBREAKER: Deterministic Fuzzing of Multi-Hart RISC-V CPUs

[3] To send an IPI, a hart cannot directly modify another hart's interrupt registers; instead it must write to a memory-mapped register managed by the CLINT using a regular memory store instruction. HARTBREAKER: Deterministic Fuzzing of Multi-Hart RISC-V CPUs

[4] The RISC-V specification requires the CLINT to support store operations of any size (byte, halfword, or word). HARTBREAKER: Deterministic Fuzzing of Multi-Hart RISC-V CPUs

[5] NaxRiscv's CLINT implementation only accepts full-word stores, incorrectly raising an exception when a program attempts to use a store-byte instruction. HARTBREAKER: Deterministic Fuzzing of Multi-Hart RISC-V CPUs

[6] The default CLINT standardized by RISC-V lacks configurability in prioritization and preemption of interrupts, motivating the RISC-V CLIC specification which enables pre-emptible, low-latency vectored interrupts. CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers