Capability Architecture

Concept

A capability architecture is a hardware/software design that augments ordinary memory references with unforgeable, bounded capability tokens to enforce fine-grained memory access control and compartmentalization. The concept is implemented in research systems such as CHERI, RISC-V-based RV-CURE, and the Morello capability-enhanced Arm prototype, and has been extended to embedded/RTOS settings to mitigate threats from application, kernel, and peripheral sources.

First seen 7/3/2026

Last seen 7/3/2026

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Capability Architecture

Overview

A capability architecture is a computer system design in which memory references are represented as capabilities: unforgeable, bounded tokens that combine an address with permissions (and typically bounds, type, and validity metadata). Capabilities are used to enforce fine-grained memory access control, support software compartmentalization, and provide strong memory-safety primitives at the hardware level. The capability-architecture concept subsumes a family of concrete designs, including the CHERI capability-system architecture, capability-enhanced instruction-set extensions for RISC-V and Arm, and token-capability approaches for embedded platforms.

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CHERI Capability Architecture ← part of 95% 1e

CHERI Capability Architecture is a specific instance of Capability Architecture.

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CITATIONS

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[1] Memory safety violations remain persistent and problematic in modern systems despite decades of mitigation effort. RV-CURE: A RISC-V Capability Architecture for Full Memory Safety

[2] RV-CURE is a RISC-V capability architecture that implements full-system support for full memory safety using a data-pointer tagging (DPT) compiler technique and lightweight BOOM-based hardware extensions. RV-CURE: A RISC-V Capability Architecture for Full Memory Safety

[3] RV-CURE achieves strong memory safety at a 10.8% slowdown across the SPEC 2017 C/C++ workloads on an FPGA prototype running Linux. RV-CURE: A RISC-V Capability Architecture for Full Memory Safety

[4] A capability-execution pipeline can be implemented in parallel with the existing memory-execution pipeline without intrusive modifications. RV-CURE: A RISC-V Capability Architecture for Full Memory Safety

[5] Existing computer-architectural defenses consider at most two of the threat vectors (application software, OS kernel, peripherals) in their security model. Trust Nothing: RTOS Security without Run-Time Software TCB (Extended Version)

[6] A token-capability approach combined with peripheral protection enables an RTOS built without a run-time software TCB by disaggregating subsystems into mutually isolated, fully untrusted components. Trust Nothing: RTOS Security without Run-Time Software TCB (Extended Version)

[7] CHERI is a hybrid capability-system architecture for scalable software compartmentalization. CHERI: A hybrid capability-system architecture for scalable software compartmentalization

[8] End-to-end formal verification has been performed for a RISC-V processor extended with capability pointers. End-to-end formal verification of a RISC-V processor extended with capability pointers

[9] Verified security has been demonstrated for the Morello capability-enhanced prototype Arm architecture. Verified security for the Morello capability-enhanced prototype Arm architecture