Data Forwarding

Concept

Data forwarding is a microprocessor pipeline technique used alongside interlocking to preserve the sequential semantics of an instruction-set architecture (ISA) while overlapping instruction execution. In pipelined designs such as the Y86-64 PIPE, forwarding paths route values produced in later pipeline stages back to earlier stages where they are consumed, reducing or eliminating certain data-hazard stalls. In industrial designs such as the e500, data forwarding is one of several micro-architectural features used for early resolution of read-after-write (RAW) data dependencies.

First seen 5/25/2026

Last seen 7/3/2026

Evidence 6 chunks

Wiki v2

WIKI

Overview

Data forwarding is a microprocessor pipeline technique used alongside interlocking to make a pipelined implementation faithfully implement the sequential semantics of an instruction-set architecture (ISA). In the cited Y86-64 verification context, the ISA is described as a sequential model in which instructions execute in strict order and affect architectural state such as registers, the program counter, and memory. Pipelined implementations improve performance by overlapping multiple instructions, and forwarding/interlocking mechanisms help preserve the same architectural result as the sequential ISA model ^[1].

Role in handling hazards

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RELATIONSHIPS

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PIPE Pipeline Processor ← uses 100% 2e

PIPE uses data forwarding to resolve hazard conditions between instructions in the pipeline.

Pipeline Hazard ← mentions 100% 1e

Data forwarding is employed to handle pipeline hazards in pipelined processors.

MIPS Processor ← mentions 85% 1e

The MIPS processor was used to generate test programs for data forwarding in prior work

LINKED ENTITIES

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MIPS Processor MENTIONS Extracted graph relationship

CITATIONS

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[1] Data forwarding is a pipeline technique used with interlocking to preserve the sequential semantics of an ISA while overlapping instruction execution. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[2] In a STALL pipeline variant, no data forwarding is used and an instruction can stall in the decode stage for up to three cycles when a later stage imposes a data hazard. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[3] In the LF variant, an added forwarding path connects the data-memory output to the pipeline register that feeds the data-memory input, allowing some load/use hazards to be resolved by forwarding. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[4] The PIPE hardware structure includes forwarding-related decode-stage blocks labeled Sel+Fwd A and Fwd B, and values such as W_valM, W_valE, M_valA, and memory output paths. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[5] Combinational forwarding dependencies impose stage ordering constraints: writeback to decode (variant SW), memory to execute (variant LF and condition code handling), memory to decode, and execute to decode. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[6] The signal m_valM computed in the memory stage feeds into the forwarding logic in the decode stage of the PIPE pipeline. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[7] In the e500 processor, data forwarding is used for early resolution of RAW data dependencies, alongside multiple issue, out-of-order execution with in-order completion, register renaming, and reservation stations. Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study

[8] Prior pipeline-path-level model partitioning has been applied to generate test programs targeting data forwarding behavior in a MIPS-based processor. Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study

[9] Four different data forwarding mechanisms are considered when validating industrial processor forwarding logic. Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study

[10] Formal verification of pipelined processors requires proving that the pipelined implementation produces the same architectural result as a sequential ISA implementation, making forwarding decisions part of the control-logic behaviors that must be accounted for. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5