Data Forwarding

Concept

Data forwarding is a pipeline technique used with interlocking to preserve the sequential semantics of an instruction-set architecture while overlapping instruction execution. In the Y86-64 PIPE context, forwarding can reduce stalls caused by some data hazards, including some load/use hazards when an added path forwards data-memory output to the pipeline register feeding data-memory input.

First seen 5/25/2026

Last seen 5/26/2026

Evidence 3 chunks

Wiki v1

WIKI

Overview

Data forwarding is a microprocessor pipeline technique used alongside interlocking to make pipelined execution faithfully implement the sequential semantics of an instruction-set architecture (ISA). In the cited Y86-64 verification context, the ISA is described as a sequential model in which instructions execute in strict order and affect architectural state such as registers, the program counter, and memory. Pipelined implementations improve performance by overlapping multiple instructions, and forwarding/interlocking mechanisms help preserve the same architectural result as the sequential ISA model.

Role in handling hazards

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RELATIONSHIPS

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PIPE Pipeline Processor ← uses 100% 2e

PIPE uses data forwarding to resolve hazard conditions between instructions in the pipeline.

Pipeline Hazard ← mentions 100% 1e

Data forwarding is employed to handle pipeline hazards in pipelined processors.

LINKED ENTITIES

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pipelining USES Extracted graph relationship

CITATIONS

6 sources

6 citations — click to expand

[1] Data forwarding is used with interlocking in pipelined microprocessors to help pipelined execution faithfully implement sequential ISA semantics. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[2] Pipelining overlaps the execution of multiple instructions, while the ISA model is sequential and defines effects on registers, program counter, and memory. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[3] In the STALL Y86-64 pipeline variant, no data forwarding is used; an instruction instead stalls in decode for up to three cycles when a downstream instruction imposes a data hazard. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[4] In the LF variant, an added forwarding path from data-memory output to the pipeline register feeding data-memory input allows some load/use hazards to be resolved by forwarding rather than stalling. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[5] The PIPE hardware figure includes forwarding-related decode-stage blocks labeled Sel+Fwd A and Fwd B. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[6] Formal verification of the pipelined processor aims to prove that every possible instruction sequence produces the same result as a purely sequential ISA implementation. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5