2026-07-02
6 items 234 entities 302 connections
Processed 24 entities and 29 relations.
LM RISC-V DV RISCV-DV SweRV EH-1 Spike Riviera-PRO RISC-V RTL UVM Random Assembly Test Generation Instruction Set Simulator Functional Coverage Code Coverage SystemVerilog Post-simulation Comparison RTL Simulation RTL Compilation Test Compilation Western Digital Google Lampro Mellon RISC-V GNU Toolchain core_integrate.sh toolchain_paths.sh sim.py
Processed 43 entities and 47 relations.
CRAVE SCV Constrained Random Verification Stimuli Generation Electronic System Level Design SystemC Transaction Level Modeling Universal Verification Methodology BDD-based Constraint Solving SAT-based Constraint Solving SMT-based Constraint Solving Portfolio Constraint Solving metaSMT Z3 MiniSAT CUDD Boolector PicoSAT SWORD AIGER Dynamic Constraint Management Inline Constraints Incremental Constraint Specification Over-constraint Analysis randv<T> rand_obj rand_vec<T> Generator System-on-Chip Five-Stage Pipeline CPU CISC CPU Program Input Generation Simulation-based Equivalence Checking RTL Bubble Sort Input Generation ALU Constraint Verification Finn Haedicke Hoang M. Le Daniel Große Rolf Drechsler University of Bremen DFKI GmbH CRAVE: An Advanced Constrained Random Verification Environment for SystemC
Processed 49 entities and 57 relations.
GENESYS Covariance Matrix Adaptation Evolution Strategy Program Synthesis Continuous Optimization Machine Programming Bin Mapping Domain Specific Language Restart Policy Neural Program Optimization DeepCoder PCCoder RobustFill PushGP NetSyn Multivariate Normal Distribution Autoencoder Genetic Programming Genetic Algorithm Single Group Mapping Multi-Group Mapping Dynamic Bin Mapping Token Probability LSTM Cumulative Step-Size Adaptation Covariance Matrix Error Function Input-Output Examples IPOP Restart Strategy BIPOP Restart Strategy Reinforcement Learning Formal Program Synthesis Stochastic Superoptimization Shantanu Mandal Todd A. Anderson Javier Turek Justin Gottschlich Abdullah Muzahid Nikolaus Hansen Texas A&M University Intel Labs Merly AI Synthesizing Programs with Continuous Optimization Shgo Syntax-Guided Synthesis FlashFill Neural Network Markov Chain Monte Carlo Beam Search Depth-First Search
Processed 45 entities and 53 relations.
Cascade DifuzzRTL TheHuzz RFUZZ Spike Yosys CPU fuzzing asymmetric ISA pre-simulation differential fuzzing program reduction control flow entanglement with data flow RISC-V program generation RISC-V instruction set architecture (ISA) RTL simulation instruction set simulator (ISS) basic block control register coverage multiplexer select coverage program non-termination as bug detection fuzzing prevalence test case completion formal verification cf-ambiguous instruction offset applier instruction privilege transitions Control and Status Registers (CSRs) Floating-Point Unit (FPU) memory management in program generation dependency chain ELF file Cascade: CPU Fuzzing via Intricate Program Generation Flavien Solt Katharina Ceesay-Seitz Kaveh Razavi ETH Zurich VexRiscv PicoRV32 Kronos CVA6 Rocket BOOM HypFuzz Cascade Python implementation differential fuzzing
\tool: Differential testing with LLMs using Natural Language Specifications and Code Artifacts
source →Processed 30 entities and 52 relations.
DiffSpec Differential Testing Prompt Chaining Large Language Model Instruction Set Architecture eBPF WebAssembly eBPF ISA Specification WebAssembly Language Specification eBPF Verifier eBPF JIT Compiler RSH Instruction Linux ARM32 eBPF Implementation ebpf-for-windows Kernel Memory Leak Fuzzing LKL-fuzzer BRF BVF Kgent DITWO WADIFF Wasmaker TitanFuzz Fuzz4All Mokav AID Wasm Validator Natural Language Specification eBPF Bytecode Test
Processed 43 entities and 64 relations.
GenHuzz Hardware-Guided Reinforcement Learning Proximal Policy Optimization whitebox fuzzing coverage-based fuzzing differential testing reinforcement learning RISC-V assembly generation RISC-V ISA RTL Device Under Test Golden Reference Model hardware coverage Physical Memory Protection finite state machine coverage test case generation language model-based fuzzer GPT-2 Spike Synopsys VCS DifuzzRTL TheHuzz ChatFuzz Cascade RocketChip Boom CVA6 fuzzing policy reward function instruction semantics transformer architecture Generative Pre-trained Transformer Byte-Pair Encoding false positive detection Load-Reserved Store-Conditional Lichao Wu Mohamadreza Rostami Huimin Li Jeyavijayan Rajendran Ahmad-Reza Sadeghi Technical University of Darmstadt Texas A&M University GenHuzz: An Efficient Generative Hardware Fuzzer