CISC CPU

Concept

A CISC CPU (Complex Instruction Set Computer central processing unit) is a processor architecture evaluated as a verification target by the CRAVE constrained-random verification environment. In the CRAVE case study, a CISC CPU is modeled at three levels of abstraction—an Instruction Set Architecture (ISA) model in C++, an OSCI TLM-2.0 SystemC transaction-level model, and a SystemC RTL model implementing a five-stage pipeline—and is verified using CRAVE-generated instruction sequences and randomized inputs.

First seen 7/2/2026

Last seen 7/2/2026

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Overview

A CISC CPU is a processor based on the Complex Instruction Set Computer paradigm. In the context of the CRAVE advanced constrained-random verification environment, a CISC CPU serves as the primary verification target, modeled at multiple levels of abstraction to enable cross-abstraction equivalence checking.

CISC CPU as a CRAVE Verification Target

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CRAVE ← evaluates 90% 1e

CRAVE is applied to verify a CISC CPU with 8 registers.

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CRAVE EVALUATES Extracted graph relationship

CITATIONS

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[1] A CISC CPU with 8 registers of 32-bit data width each is verified using CRAVE. CRAVE: An Advanced Constrained RAndom VErification Environment for SystemC

[2] The CISC CPU implements a subset of the IA-32 architecture including load/store, arithmetic, jump and halt instructions. CRAVE: An Advanced Constrained RAndom VErification Environment for SystemC

[3] The CISC CPU is available at three levels of abstraction: an ISA model in C++, a SystemC TLM model using OSCI TLM-2.0, and a SystemC RTL model implementing a five-stage pipeline. CRAVE: An Advanced Constrained RAndom VErification Environment for SystemC

[4] CRAVE is used to generate programs (instruction sequences) and their inputs, which are used as stimuli for all three CISC CPU models. CRAVE: An Advanced Constrained RAndom VErification Environment for SystemC

[5] The verification scenario described for the CISC CPU involves a bubble sort instruction sequence with randomized inputs under constraints ensuring the array fits into CPU memory and does not collide with the loaded program. CRAVE: An Advanced Constrained RAndom VErification Environment for SystemC