Overview
A CISC CPU is a processor based on the Complex Instruction Set Computer paradigm. In the context of the CRAVE advanced constrained-random verification environment, a CISC CPU serves as the primary verification target, modeled at multiple levels of abstraction to enable cross-abstraction equivalence checking.
CISC CPU as a CRAVE Verification Target
According to the CRAVE paper, a CISC CPU is applied as a verification case study with the following architectural characteristics:
- Register file: 8 registers, each 32 bits wide.
- Instruction set: A subset of the IA-32 architecture, including load/store, arithmetic, jump, and halt instructions.
- Pipeline: A five-stage pipeline is implemented in the RTL model.
The CISC CPU is available at three levels of abstraction:
- An Instruction Set Architecture (ISA) model written in C++.
- A SystemC TLM model using OSCI TLM-2.0.
- A SystemC RTL model implementing a five-stage pipeline.
Verification Methodology with CRAVE
CRAVE is used to generate both:
- Programs (instruction sequences), and
- Program inputs,
which together serve as stimuli for all three abstraction-level models. The generated stimuli then feed a simulation-based equivalence-checking approach across models at different levels of abstraction.
A concrete scenario described is the verification of an instruction sequence implementing the bubble sort algorithm, where the input is randomized under constraints that ensure the array fits in CPU memory, does not collide with the loaded program, and is nearly non-increasing (making the sort challenging).
Evaluation Role
The CISC CPU is the design under verification in the CRAVE paper—i.e., the entity that CRAVE evaluates. The relationship is directional: CRAVE → CISC CPU (EVALUATES), with CISC CPU being the design being verified by the tool.
Related Concepts and Tools
- IA-32 architecture: The CISC CPU implements a subset of IA-32 instructions (load/store, arithmetic, jump, halt).
- OSCI TLM-2.0: Transaction-level modeling standard used for the CISC CPU's TLM abstraction.
- Five-stage pipeline: The RTL implementation depth of the CISC CPU.
- SystemC RTL: The lowest-level model of the CISC CPU used in CRAVE verification.
- Bubble sort: The algorithm whose implementation is verified as a concrete scenario.