2026-07-01
6 items 191 entities 225 connections
Processed 17 entities and 18 relations.
MISHEGOS Differential Fuzzing x86-64 Instruction Decoding Difference Oracle Sliding Window Fuzzing Strategy Overapproximated Machine Instruction Model Variable-Length Instruction Architecture Decoding Discrepancy Differential Analysis of x86-64 Instruction Decoders William H. Woodruff Niki Carroll Sebastiaan Peters Trail of Bits George Mason University Eindhoven University of Technology x86-64 N-Version Disassembly
Processed 42 entities and 54 relations.
System on Chip (SoC) Constrained Random Verification (CRV) Directed Verification Functional Coverage Random Stimulus Generation Design Under Test (DUT) AXI Protocol Cache Coherency Stashing RTL Simulation Backdoor Access Front Door Access Coverage-Driven Verification Cross Coverage Stimulus Base Class Transaction-Level Modeling Coverage Closure Regression Testing Automatic Test Pattern Generation L1/L2 Cache Constraint-Based Stimulus Generation Weight-Based Transaction Control Randomized Delay Injection Data Comparison via Backdoor Read Unaligned Address Testing Bus Arbitration Verification AXI Transaction ID Randomization Seed-Based Regression Grading SystemVerilog parameters.txt random_axi stimulus class Test Directive Generation for Functional Coverage Closure Using Inductive Logic Programming Constraint-Based Random Stimuli Generation for Hardware Verification Applying Constrained-Random Verification to Microprocessors Coverage Driven Constraint Random Verification Architecture Bug hunting SoC designs to achieve full functional coverage closure Vijeta Marwah Saurabh Mishra Freescale Semiconductor National Institute of Technology, Kurukshetra Uttar Pradesh Technical University Lucknow VEDANT Semiconductor
Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States
source →Processed 31 entities and 38 relations.
DIG (Dynamic Instruction Generator) Dynamic Instruction Generation Functional Verification Random Instruction Generation RISC-V DV RISC-V Torture Instruction Set Simulator Processor Runtime Architectural State Test Instruction Stream Functional Coverage Intra-instruction Test Knowledge Inter-instruction Test Knowledge RISC-V VeeR EH2 Western Digital Zhejiang University HEXIN Technologies Co., Ltd Anlin Liu T.C. Lu Yuhao Xi Yangfan Liu Peng Liu MicroGP Genesys-Pro Constraint Satisfaction Problem (CSP) for Test Generation Coverage Directed Test Generation Bayesian Networks for Test Generation Evolutionary Assembly Program Generation SMT-solver State Generation Dark Instructions and Vulnerabilities Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States
Processed 23 entities and 26 relations.
Genesys Covariance Matrix Adaptation Evolution Strategy Program Synthesis Continuous Optimization Evolutionary Algorithm Grammatical Evolution Genetic Programming Restart Policy Mapping Scheme Shantanu Mandal Todd A. Anderson Javier S. Turek Justin Gottschlich Abdullah Muzahid Texas A&M University Intel Santa Clara University The three pillars of machine programming Program synthesis as latent continuous optimization PSB2 CMA-ES for one-class constraint synthesis Deduction-Guided Reinforcement Learning Conflict-Driven Learning
Processed 54 entities and 63 relations.
RISCSmith Cascade RISCV-DV Spike Verilator DIFUZZRTL DLFuzz TheHuzz MorFuzz INSTILLER RISC-V RTL Hardware Fuzzing Differential Testing On-the-fly Differential Analysis Rich Instruction Construction Instruction Modeling Constrained Random Instruction Generation Coverage-Guided Fuzzing Source Instrumentation Binary Search-Based Minimization Exception Carry-on Template Per-Instruction Logging UVM Formal Verification Pre-Silicon Verification NaN Boxing Strongly Typed Instruction Model Inter-Instruction Dependency Register and Memory Initialization RISC-V UnifiedDB GNU RISC-V Toolchain CPU PicoRV32 CVA6 VexRiscv Rocket XiangShan Kronos BOOM RISCSmith: Finding RISC-V CPU Bugs via Rich Instruction Construction and On-the-fly Differential Analysis Xudong Zhang Yuanliang Chen Zehong Yu Zhen Yan Fuchen Ma Dalong Shi Yu Jiang Tsinghua University Aviation Industry Corporation of China CHIPS Alliance OpenHW Group OpenXiangShan lowRISC
Processed 24 entities and 26 relations.
GoldenFuzz: Generative Golden Reference Hardware Fuzzing GoldenFuzz hardware fuzzing Golden Reference Model ISA-compliant test generation instruction block concatenation feedback-driven fuzzing coverage-guided fuzzing digital twin simulation two-stage fuzzing framework Device Under Test CVSS vulnerability scoring hardware vulnerability discovery RocketChip BOOM CVA6 BA51-H RISC-V Lichao Wu Mohamadreza Rostami Huimin Li Nikhilesh Singh Ahmad-Reza Sadeghi TU Darmstadt