LM RISC-V DV

Tool

First seen 7/2/2026

Last seen 7/2/2026

Evidence 2 chunks

NEIGHBORHOOD

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19 connections

SweRV EH-1 uses → 1e

LM RISC-V DV integrates the SweRV EH-1 core from Western Digital.

riscv-dv uses → 1e

LM RISC-V DV uses RISCV-DV as its random assembly test generator.

spike uses → 1e

LM RISC-V DV uses Spike as the Instruction Set Simulator for post-simulation comparison.

LM RISC-V DV requires the RISC-V GNU Toolchain as a dependency.

Riviera-PRO uses → 1e

LM RISC-V DV supports Riviera-PRO as an SV/UVM simulator.

RTL simulation implements → 1e

LM RISC-V DV implements RTL Simulation as part of its verification flow.

RTL Compilation implements → 1e

LM RISC-V DV implements RTL Compilation as part of its verification flow.

Test Compilation implements → 1e

LM RISC-V DV implements Test Compilation for both random and directed tests.

LM RISC-V DV implements random assembly test generation.

LM RISC-V DV implements post-simulation comparison with the ISS.

Functional Coverage implements → 1e

LM RISC-V DV supports extraction of functional coverage.

Code Coverage implements → 1e

LM RISC-V DV implements code coverage report generation.

Lampro Mellon authored by → 1e

LM RISC-V DV is authored by Lampro Mellon.

LM RISC-V DV uses an Instruction Set Simulator (Spike) for verification.

RTL uses → 1e

LM RISC-V DV uses RTL sources for simulation and compilation.

core_integrate.sh ← part of 1e

core_integrate.sh is part of the LM RISC-V DV repository scripts.

toolchain_paths.sh is part of the LM RISC-V DV repository scripts.

sim.py ← part of 1e

sim.py is part of the LM RISC-V DV integration files.

RISC-V uses → 1e

LM RISC-V DV is a verification environment targeting the RISC-V architecture.