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RISC-V Core & SoC Verification: A New Normal in Verification Techniques

Verification Futures Reading 2024 Adnan Hamid

A Look At RISC-V

Open Instruction Set Architecture (ISA) gaining significant traction in multiple applications
Significant verification challenges
- Arm spends $150M per year on 10¹⁵ verification cycles per core
- Hard for RISC-V development group to achieve this same quality
- Lots of applications expands verification requirements
- Requires automation, reuse and new thinking
RISC-V International developing certification committee to certify devices against architectural compliance tests

Meeting RISC-V Verification Challenges

BREKER

Reuse & automation to meet quality expectation
- Automated test generation key
RISC-V special requirements
- Custom instruction verification
- Compliance assurance
- Broad range of architectures
Different processors have different needs
- Embedded cores
- Processor clusters
- Application processors

Suggested RISC-V verification “stack”

Different Challenges for Core vs SoC Verification

RISC-V Core Verification Challenges

tbl-0.md

RISC-V SoC Verification Challenges

tbl-1.md

Breker Background:

Test Suite Synthesis for RISC-V Cores & SoCs

BREKER

Breker is a key, longstanding part of the verification ecosystem for processors and SoCs based on x86 and Arm architectures
Breker has become part of the verification ecosystem for processors and SoCs based on RISC-V architectures
- Working with multiple RISC-V developers and users/integrators
RISC-V has room to grow if we solve the verification barrier
- We are experienced in x86 and Arm verification, now are sharing this experience with RISC-V teams through automated tests

The Breker SystemVIP Library

Core Integrity FastApps
RISC-V System Integrity TrekApp
ARM System Integrity TrekApp
Cache Coherency TrekApp 2.0
Firmware-First TrekApp
Power Management TrekApp
Security TrekApp
Networking TrekApp

Constrained Random vs AI Planning Algorithm Synthesis

BREKER

Crossing RISC-V Core Verification Components

BREKER

Concurrent Test Execution

BREKER

Core-Integrity Challenges

tbl-2.md

RV64 Core Instruction Generation

BREKER

Instruction Coverage Analysis

BREKER™

27/103 reachable opcode have been exercised

Atomics, loads and stores not reachable in register only test

RV64 Core Load/Store

BREKER

Locality of write adds

RV64 Core Exception Testing

BREKER

Page Based Virtual Memory Tests

BREKER

RV64 Core Page Based MMU Tests

BREKER™

Swap MMU PTE's and Check memory access

Core-Integrity: Single Core, 4 Threads

Tests utilizes processor's available resources/software threads

Testing a Custom Instruction

BREKER

RISC-V ISA custom instructions pose a particularly difficult verification challenge
Custom instructions need to be tested with the processor tests, not as an afterthought
Breker solution allows custom instruction tests to be easily added into test graph
Breker synthesis combines these tests with the app to ensure full custom processor testing

SoC-Integrity Challenges

BREKER

tbl-3.md

Breker RISC-V SoC-Integrity SystemVIP

End-to-End use cases
Early Firmware Testing
Performance-Power Profiling

RISC-V SoC Integrity TrekApp

BREKER

RV64 MultiCore MoesiStates

BREKER™

Planned Cache State Transitions

Atomics Testing

[LOGO]

BREKER™

Check result is aggregate of synchronized atomic operations

Dekker Memory Ordering

BREKER™

False-Share Memory Stress Tests

BREKER™

int trek_microloop_write_check8( void * addrs[], int count, trek_sint8_t pattern) { int errorCount = 0; int ii; for ( ii = 0; ii < count; ++ii) { trek_write(pattern, addrs[i]); } for ( ii = 0; ii < count; ++ii) { if (trek_reads(addrs[i]) != pattern) { ++errorCount; trek_runtime_error("trek_microloop_write_check8", addrs[i], pattern, trek_reads(addrs[i])); }; } return errorCount;

for ( int ii = 0; ii < 1000; ++ii ) { errorCount += trek_microloop_write_check8(addrs, 4, 184); }

Each core has free running loop

High Coverage and Bug Hunting

BREKER

Recent examples of bugs discovered in real designs

RISC-V spec misunderstanding between core vendor and user
Coherent Mesh Network (CMN) programming issues
Misconfigured ARM CMN pin to enable coherent traffic
DDR model unable to handle AXI "wrap" transactions.
Common cache line access reveals deadlock
Custom instruction bugs discovered by stress tests
Results mismatch with ultrawide address strides
Incorrect exception for guest virtual address[63:38] = 0x1ffffff
Bad mcause value for guest physical address[63:31] != 0x0

SystemVIP Test Suite Synthesis Coverage Comparison

Typical directed coherency coverage

... vs. Breker automated coherency tests

Thanks for Listening! Any Questions?