AXI Wrap Transactions
ConceptAXI wrap transactions are a type of bus transaction referenced in verification case studies. They have been identified as a source of real-world bugs, notably in DDR memory models that proved unable to handle them, and they are mentioned in the context of DDR Memory Model Verification efforts.
First seen 7/6/2026
Last seen 7/6/2026
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AXI Wrap Transactions
Overview
AXI wrap transactions are a category of bus transactions referenced in processor and SoC verification literature. They appear in discussion of cross-component verification challenges, where bus-protocol transaction types must be correctly modeled by downstream memory subsystem components such as DDR memory models.
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1 connectionsA bug was discovered where the DDR model was unable to handle AXI wrap transactions.
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[1] A DDR model was found to be unable to handle AXI 'wrap' transactions, listed as a recent example of bugs discovered in real designs. RISC-V Core & SoC Verification
[2] AXI wrap transactions are surfaced in the broader context of RISC-V Core & SoC verification case studies covering core integrity, coherency, atomics, memory ordering, and memory stress testing. RISC-V Core & SoC Verification