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AXI Wrap Transactions

Concept WIKI v1 · 7/6/2026

AXI wrap transactions are a type of bus transaction referenced in verification case studies. They have been identified as a source of real-world bugs, notably in DDR memory models that proved unable to handle them, and they are mentioned in the context of DDR Memory Model Verification efforts.

AXI Wrap Transactions

Overview

AXI wrap transactions are a category of bus transactions referenced in processor and SoC verification literature. They appear in discussion of cross-component verification challenges, where bus-protocol transaction types must be correctly modeled by downstream memory subsystem components such as DDR memory models.

Verification Challenges

In documented verification case studies, AXI wrap transactions have surfaced as a concrete source of bugs discovered in real designs. Specifically, the following issue has been reported:

  • DDR model unable to handle AXI "wrap" transactions — a DDR memory model failed to correctly process AXI wrap transactions, representing a gap between the bus-level transaction protocol and the memory model's transaction-handling capability.

This finding is recorded among a broader set of "Recent examples of bugs discovered in real designs" uncovered during RISC-V core and SoC verification activities.

Relationship to DDR Memory Model Verification

The handling of AXI wrap transactions is explicitly mentioned as a concern within DDR Memory Model Verification. Because DDR memory models must accept and correctly reflect all transaction types generated by system initiators (including wrap-type bursts), any inability to do so constitutes a fidelity gap in the memory model. Verification efforts targeting DDR memory models therefore need to exercise AXI wrap transactions as part of their stimulus coverage to guard against this class of bug.

See Also

LINKED ENTITIES

1 links
DDR Memory Model Verification MENTIONS

CITATIONS

2 sources
2 citations
[1] A DDR model was found to be unable to handle AXI 'wrap' transactions, listed as a recent example of bugs discovered in real designs. RISC-V Core & SoC Verification
[2] AXI wrap transactions are surfaced in the broader context of RISC-V Core & SoC verification case studies covering core integrity, coherency, atomics, memory ordering, and memory stress testing. RISC-V Core & SoC Verification