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STIMSMITH

Synopsys VC Formal

Tool
First seen 7/6/2026
Last seen 7/11/2026
Evidence 2 chunks

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RELATIONSHIPS

6 connections
SystemVerilog Assertion uses → 100% 1e
Synopsys VC Formal supports SystemVerilog Assertions.
μARCHIFI: Formal Modeling and Verification Strategies for Microarchitectural Fault Injections ← mentions 90% 1e
The paper mentions Synopsys VC Formal as a commercial tool supporting SystemVerilog Assertions.
ZP Cosim ← uses 96% 1e
ZP Cosim uses Synopsys VC Formal for unreachability analysis of coverpoints
unreachability analysis implements → 96% 1e
Synopsys VC Formal implements formal unreachability analysis for coverpoints via its Formal Coverage Analyzer
SAT solver uses → 88% 1e
Synopsys VC Formal uses constraint/SAT solvers to determine unreachability
formal verification implements → 92% 1e
Synopsys VC Formal implements formal verification including coverage analysis