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RISC-V International

Organization

RISC-V International is a non-profit organization that serves as the home of the open standard RISC-V Instruction Set Architecture (ISA), its related specifications, and its stakeholder community. It is responsible for stewarding the standardization, adoption, and verification of the RISC-V ISA within a modular, extensible, and open ecosystem.

First seen 5/27/2026
Last seen 8/28/2026
Evidence 29 chunks
Wiki v3

WIKI

Overview

RISC-V International is a non-profit organization that serves as the home of the open standard RISC-V Instruction Set Architecture (ISA), its related specifications, and its stakeholder community. [C1]

The organization is identified in the available evidence as having been formed in 2015 to further the standardization and adoption of the RISC-V ISA. The same source describes the RISC-V project as originating at the University of California, Berkeley in 2010, with the first RISC-V specifications made public in 2011. [C2]

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NEIGHBORHOOD

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RELATIONSHIPS

15 connections
spike ← published by 100% 3e
Spike is the official RISC-V golden reference simulator maintained by RISC-V International.
RISC-V mentions → 100% 3e
RISC-V International now manages the RISC-V standard.
RISC-V profiles introduces → 95% 2e
RISC-V International ratifies and publishes profiles that define standardised behaviour subsets.
RISC-V ← mentions 98% 2e
RISC-V International is the nonprofit organization that serves as caretaker of the RISC-V instruction set.
Compliance Assurance implements → 92% 1e
RISC-V International is developing a certification committee focused on compliance assurance for RISC-V devices.
RISC-V Debug Specification ← published by 97% 1e
The RISC-V Debug Specification is published by RISC-V International.
RISC-V Instruction Set Manual Volume I ← published by 97% 1e
The RISC-V Instruction Set Manual Volume I is published by RISC-V International.
Architectural Compliance Testing implements → 95% 1e
RISC-V International is developing a certification committee to certify devices against architectural compliance tests.
RISC-V introduces → 95% 1e
RISC-V International is the governing body that ratifies the RISC-V ISA.
riscv-arch-test ← authored by 88% 1e
riscv-arch-test is maintained under RISC-V on GitHub, associated with RISC-V International.
RISC-V Control Transfer Records introduces → 88% 1e
The RISC-V Control Transfer Records extension is defined by RISC-V International as indicated by the official GitHub reference.
Physical Memory Protection (PMP) ← mentions 97% 1e
RISC-V International ratified the PMP specification
RISC-V ISA implements → 97% 1e
RISC-V International serves as the non-profit steward and home of the open standard RISC-V ISA and related specifications.
sail-riscv ← published by 100% 1e
Sail RISC-V is the formal specification adopted by RISC-V International.
vendor extension naming convention mentions → 88% 1e
RISC-V International defines vendor extension naming conventions in its toolchain conventions.

LINKED ENTITIES

1 links
RISC-V ISA IMPLEMENTS Extracted graph relationship

CITATIONS

11 sources
11 citations — click to expand
[1] RISC-V International is the non-profit home of the open standard RISC-V Instruction Set Architecture (ISA), related specifications, and stakeholder community. How do we push RISC-V CPU verification to the next level?
[2] RISC-V International was formed in 2015 to further the standardization and adoption of the RISC-V ISA, which originated at UC Berkeley in 2010 with the first specifications made public in 2011.
[3] RISC-V is provided under royalty-free open-source licenses and has been adopted across sectors, with companies developing processors and SoCs based on RISC-V.
[4] RISC-V International has expanded to more than 200 members, including Google, Qualcomm, NVIDIA, IBM, and Western Digital.
[5] The RISC-V ecosystem is open, collaborative, modular, and extensible, promoting reuse of shared tools and development resources.
[6] RISC-V has a modular design of alternative base parts plus optional extensions developed collectively by industry, research, and education, with standard extensions specified to interoperate without conflict.
[7] RISC-V International has announced several new extensions, and the ISA encourages users to develop their own extensions and modifications.
[8] Maintaining a robust and standardized ISA while accommodating diverse extensions and implementations creates challenges important to address in order to prevent fragmentation.
[9] Developing RISC-V extensions can be comparatively fast while verifying them is not; many teams underestimate processor verification by focusing only on instruction execution while difficult issues arise in microarchitecture and pipeline behavior.
[10] RISC-V International has publicly raised the question of how to push RISC-V CPU verification to the next level. How do we push RISC-V CPU verification to the next level?
[11] RISC-V's modular ISA structure allows a base instruction set to be extended with optional capabilities such as the compressed instructions extension, and the RVGC combination includes a base, the G extensions, and the C extension for general-purpose OS support.