Branch Prediction Unit

Concept

A Branch Prediction Unit (BPU) is a hardware component within a processor's instruction fetch pipeline that predicts the outcomes and targets of branch instructions to keep the pipeline supplied with instructions despite control-flow uncertainty. Modern BPUs are known to be susceptible to collision-based transient execution attacks and side-channel threats, motivating research into secure BPU designs such as STBPU and CIBPU. BPUs are also a standard block targeted during functional verification of RISC-V cores using UVM-based environments.

First seen 7/6/2026

Last seen 7/6/2026

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Branch Prediction Unit (BPU)

Overview

A Branch Prediction Unit (BPU) is a hardware structure inside a microprocessor's instruction fetch stage that speculates on the direction and target of branch instructions before they are resolved. By predicting outcomes in advance, the BPU keeps the pipeline fed with instructions, avoiding stalls that would otherwise occur when the processor must wait for a branch condition to be evaluated ^[1].

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CITATIONS

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[1] The BPU is one of the discrete blocks verified in a UVM-based RISC-V core verification environment alongside IFU, decode, execution, register file, CSRs, and LSU. Verification Of Risc-V Core Blocks Using Uvm

[2] Modern BPUs have faced numerous security threats exploiting branch instruction collisions, ranging from side-channel leakage to malicious speculative execution. STBPU: A Reasonably Secure Branch Prediction Unit

[3] STBPU customizes data representation inside the BPU per isolated software entity and monitors prediction-related events to prevent brute-force collision attacks. STBPU: A Reasonably Secure Branch Prediction Unit

[4] Prior physical-isolation SBPU schemes offer limited security and degrade prediction capability, while encryption-based SBPU schemes with periodic key re-randomization can be compromised and carry notable overhead. CIBPU: A Conflict-Invisible Secure Branch Prediction Unit

[5] CIBPU uses redundant storage, load-aware indexing, replacement design, and an encryption mechanism that does not require periodic key updates to make branch conflicts invisible to attackers. CIBPU: A Conflict-Invisible Secure Branch Prediction Unit

[6] CIBPU implemented in a RISC-V core model in gem5 reports average performance overhead of 1.12%-2.20%, and a SonicBOOM FPGA implementation reports about 2.01% average degradation. CIBPU: A Conflict-Invisible Secure Branch Prediction Unit

[7] Verification of the BPU must confirm correct branch-prediction behaviour under varied control-flow scenarios and validate pipeline interactions including forwarding, stalling, and flushing. Verification Of Risc-V Core Blocks Using Uvm