2026-08-07
6 items 275 entities 380 connections
https://riscv-europe.org/summit/2023/media/proceedings/posters/2023-06-07-Fatima-SALEEM-abstract.pdf
source →Processed 53 entities and 58 relations.
RISC-V Vector Extension RVV Specification v1.0 RVV Specification v0.9 Architecture-level Verification Vector Instruction Test Suite VLEN LMUL SEW Signature-based Checking Self-Checking Tests Instruction Set Architecture Compliance Testing Random Instruction Generation Automatic Test Generation Imperas Vector Test Suite riscvOVPsim RIOS Labs Vector Test Generator RISCOF RISC-V Torture RISC-V DV FORCE-RISCV Yang's Vector Test Generator Tenstorrent Vector Test Suite Spike ISA Simulator Sail ISA Simulator Handcar ISS Whisper ISS RISCV-ISAC Renode UVM-based Random Instruction Generation Instruction Sequence Generation Coverage-driven Verification GoLang Test Generator Scala-based Test Generator 10xEngineers Imperas RIOS Labs Andes Google Antmicro PLCT Lab Tenstorrent chipsalliance openhwgroup Fatima Saleem Umer Imran Quswar Abid Kamran Malik Yang Liu Open-Source RISC-V Vector Test Suites: A Comparative Analysis RTL Verification RISC-V ISA Vector Register GNU Make
Processed 25 entities and 29 relations.
Coverage-Guided Fuzzing Co-Simulation Virtual Prototype Transaction Level Modeling RTL RISC-V Platform Level Interrupt Controller RISC-V VP LLVM libFuzzer Verilator SpinalHDL Tracalyzer TLM-RTL Transactor Design Under Verification Cross-Level Verification Coverage Metric FreeRTOS Sallar Ahmadi-Pour Muhammad Hassan Rolf Drechsler University of Bremen DFKI GmbH Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation System-on-Chip Coverage-Guided Fuzzing Co-Simulation
Processed 58 entities and 115 relations.
Design and Application of a Co-Simulation Framework for Chisel Ryan Lund Borivoje Nikolic Krste Asanovic Anson Tsai John Wright Paul Rigge Vighnesh Iyer University of California, Berkeley Co-Simulation Framework for Chisel (CFC) Chisel ChiselTest Chipyard Gemmini Spike FireSim Dromajo Vitis HLS ISim HDL Verifier Rocket Chip BOOM Protocol Buffers (protobufs) Co-Simulation Instruction-Accurate Simulation RTL Simulation Mixed-Abstraction Verification Mixed-Signal Verification Mixed-Medium Verification Cycle-Accurate Simulation Phase-Accurate Simulation Pre-Silicon Verification Tandem Simulation Out-of-Context Elaboration Diplomacy Parameter Negotiation Stimulus Generation Interprocess Communication (IPC) via Named Pipes Binary Caching Design Space Exploration RoCC Interface RISC-V ISA FPGA Emulation Protobuf-to-Bundle Conversion Bundle-to-Protobuf Conversion ProtoToBundle BundleToProto BundleToJson PipeDriver PipeMonitor CosimTester Trait getVerifParameters VerifRoCCStandaloneWrapper CosimTestUtils.scala VerifRoCCStandalone.scala Mathworks Xilinx Esperanto Technologies Google
Processed 57 entities and 81 relations.
RISC-V Compliance Testing Negative Testing Positive Testing Coverage-Guided Fuzzing LLVM libFuzzer Test Program Generation Instruction Set Architecture (ISA) RTL Simulation UVM Constrained-Random Test Generation RISCV-DV riscvOVPsim Spike RISC-V VP GRIFT sail-riscv riscv-formal OneSpin 360 DV RISC-V Verification App RISC-V Torture Test Generator MicroTESK Fuzzing-Based Test-Suite Generation Custom Coverage Metric Custom Fuzzing Mutator Static Analysis Filter Bytestream Test-Case Template Compliance Signature Hash-Based Coverage Structural and Value Coverage Rules Instruction Decoder Verification Illegal Instruction Handling Control and Status Registers (CSRs) Privileged ISA ELF Format Constraint Solving Bayesian Network-Based Test Generation Machine Learning-Based Test Generation Model Checking Abstract Local Execution Instruction Set Simulator (ISS) Virtual Prototype Clang Compiler Instrumentation Vladimir Herdt Daniel Große Rolf Drechsler DFKI GmbH University of Bremen Imperas UC Berkeley Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side RV32I RV32IMC RV32GC Trap Handler Verilator Genesys-Pro
Interpretation of RISC-V Paper: A Semantic-Aware Hardware Acceleration Co-Simulation Verification Framework for Processor Cores - Boardor
source →Processed 36 entities and 43 relations.
DiffTest DiffTest-H Differential Testing Co-simulation Semantic-Aware Communication RTL Simulation Hardware-Accelerated RTL Simulation Batch Packaging Squash Compression Replay Debugging Structural Semantics Sequential Semantics Behavioral Semantics Verification Event Software-Hardware Communication Overhead Agile Verification NEMU ENCORE Fromajo Palladium FPGA RISC-V RTL DiffTest-H: Toward Semantic-Aware Communication in Hardware-Accelerated Co-Simulation Xiangshan MICRO 2022 Paper Yu Zihao Shi Kan Bao Yungang Institute of Computing Technology, Chinese Academy of Sciences Beijing Open Source Chip Research Institute Xiangshan Team Xiangshan Processor Design Under Test Reference Model Architectural State PCIe
Rapid Fault Injection Simulation by Hash-based Differential Fault Effect Equivalence Checks
source →Processed 46 entities and 54 relations.
Fault Injection Simulation Hash-based Differential Fault Effect Equivalence Check (CDIF+FEEC) Checkpoint Restore Boot (CRB) Statistical Fault Injection (SFI) Fault Equivalence Pruning (FEP) Dynamic Fault Collapsing (DFC) Mixed-level Simulation (MLS) Checkpoint Masking (CMSK) Checkpoint Differential (CDIF) Fault Effect Equivalence Check (FEEC) Register Transfer Level (RTL) Instruction Set Simulator (ISS) Instruction Set Architecture (ISA) Single Event Upset (SET) Silent Data Corruption (SDC) Detectable Unrecoverable Error (DUE) Database of Diffs (DoD) Database of Diff Hashes (DoH) Fault Space flip-flop-level fault injection Fault Outcome Prediction (FOP) Coordinate List Format (COO) ISO 26262 Verilator vRTLmod verilated RTL (vRTL) ARCHIE ETISS-ML EmbenchTM cv32e40p RISC-V System on Chip (SoC) micro-architectural state Johannes Geier Leonidas Kontopoulos Daniel Mueller-Gritschneder Ulf Schlichtmann L. Berrojo Technical University of Munich TU Wien OpenHW Group Rapid Fault Injection Simulation by Hash-based Differential Fault Effect Equivalence Checks server-client simulation framework golden reference simulation Hamming Weight collision-free hash function