Overview

Illegal instruction handling is a verification concern for both RISC-V instruction set simulators and RTL processor implementations in the provided evidence. The evidence emphasizes that allowing test generators to create illegal instructions helps exercise behavior that valid instruction-stream generators, compilers, or assemblers may avoid. In the ISS fuzzing work, illegal instructions were explicitly useful for thoroughly checking the instruction decoder, and the approach exposed an error in the RISC-V reference simulator Spike. [decoder_stress]

The same ISS evidence argues that coverage-guided fuzzing retains the ability to generate completely random instructions, which helps cover rare corner and error cases that may be masked by a compiler or assembler. It contrasts this with RISC-V Torture, described there as generating only valid instruction sequences and therefore unable to detect some errors found by the fuzzer. [random_illegal_value]