Binary Caching

Concept

Binary Caching is an optimization within the Co-Simulation Framework for Chisel (CFC) that reuses an existing ChiselTest simulation binary across test runs when the underlying Chisel source has not changed, avoiding the per-run rebuild cost of the standard ChiselTest flow and yielding substantial test runtime speedups.

First seen 8/7/2026

Last seen 8/7/2026

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Binary Caching

Overview

Binary Caching is a performance optimization used by the Co-Simulation Framework for Chisel (CFC). It addresses a key pain point in accelerator integration testing inside Chipyard-style flows: every ChiselTest run in the default paradigm rebuilds the simulation binary from scratch, even when the RTL under test has not changed. By reusing a previously built simulation binary when the underlying Chisel code is unchanged, Binary Caching eliminates redundant elaboration and compilation work between test runs.

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Design and Application of a Co-Simulation Framework for Chisel ← uses 100% 2e

CFC introduces binary caching as an optimization to speed up test runs.

Co-Simulation Framework for Chisel (CFC) ← uses 100% 2e

CFC introduces binary caching to avoid rebuilding simulation binaries between test runs.

ChiselTest ← uses 85% 1e

Binary caching is introduced as an optimization for ChiselTest.

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Design and Application of a Co-Simulation Framework for Chisel USES Extracted graph relationship

Co-Simulation Framework for Chisel (CFC) USES Extracted graph relationship

ChiselTest USES Extracted graph relationship

CITATIONS

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[1] Binary Caching allows an existing simulation binary to be reused if the underlying Chisel code has not changed between test runs, in contrast with the default ChiselTest paradigm which rebuilds the simulation binary for every test run. Design and Application of a Co-Simulation Framework for Chisel

[2] As a result, CFC uses the same number of simulator builds as a full-SoC simulation approach, while offering significant speedups in both build and run times. Design and Application of a Co-Simulation Framework for Chisel

[3] With the additional optimization of ChiselTest binary caching, tests on Gemmini show the potential for up to 9.72x speedup in test run time compared to a full-SoC RTL simulation. Design and Application of a Co-Simulation Framework for Chisel

[4] Binary Caching is presented as Section 3.5 of the thesis under the heading 'Optimization - ChiselTest Binary Caching.' Design and Application of a Co-Simulation Framework for Chisel

[5] In Chipyard, full-SoC RTL simulation of compiled C-based test binaries is slow; simulator elaboration can take 15 minutes to several hours, and each run adds tens of minutes, motivating both CFC's co-simulation approach and Binary Caching. Design and Application of a Co-Simulation Framework for Chisel