2026-08-06
4 items 125 entities 181 connections
Processed 26 entities and 57 relations.
BNF Grammar Type System Type Variable Type Quantifier Kind Annotation Pattern Matching Expression Language Register Type Bitfield Type Effect System Function Definition Mapping Definition Struct Type Enum Type Union Type Overload Definition Instantiation Scattered Definition Termination Measure Let Binding Attribute Annotation Vector Type Bitvector Literal Value Specification Extern Binding Sail ISA Specification Language
Processed 43 entities and 52 relations.
Simulation-based Verification Constraint-based Stimuli Generation Minimal Stimuli Generation Coverage-driven Verification Functional Coverage Boolean Satisfiability (SAT) SAT-based Stimuli Generation Tseitin Transformation Iterative Stimuli Generation Naive Stimuli Generation Random Constraint-based Simulation Parallel Simulation for Multiple Scenarios Boolector Algorithm 1: Minimal Stimuli Generation Design Under Verification (DUV) Coverage Metrics Scenario-based Verification RISC Processor Program Counter (PC) Arithmetic Logic Unit (ALU) Control Unit (CU) Memory Management Unit (MMU) ALU Reduced External Data Memory (RAM) Stack Harvard Architecture SMT-based Stimuli Generation Bounded Model Checking Automatic Constraint Generation Random Stimulus Generation Coverage-driven Stimuli Generation (Yang et al., 2012) HW/SW Co-Verification using Bounded Model Checking (Große et al., 2006) SMT-based Stimuli Generation in SystemC Verification Library (Wille et al., 2009) Automatic Constraint Generation for Guided Random Simulation (Yeh & Huang, 2010) Shuo Yang Robert Wille Daniel Große Rolf Drechsler University of Bremen DFKI GmbH solvertec GmbH SystemC Verification Library Problem Encoding for SAT
Research on functional verification method processor model built by Chisel | Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University
source →Processed 19 entities and 19 relations.
Chisel ARM V4 ISA ARMChisel Random Instruction Generator Functional Verification Coverage-Driven Verification Direct Test Verification FPGA Acceleration Test Stimulus Generation Processor Model Verification RTL Verilog Instruction Set Architecture Research on functional verification method processor model built by Chisel Lening WU Miao WANG Fu CHEN AVIC Xi'an Aeronautics Computing Technique Research Institute Northwestern Polytechnical University
ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard
source →Processed 37 entities and 53 relations.
ConfigDrivenV Universal Verification Methodology (UVM) Constrained Random Test Generation Golden Reference Model Self-Checking Scoreboard RTL Verification Python-UVM Co-Verification 16-bit RISC Processor UART Controller SystemVerilog Python ModelSim Intel FPGA Starter Edition Bug Injection Functional Verification Coverage-Driven Verification File I/O Bridge (Python to UVM via $fscanf) Two-Layer Verification Architecture RISC-V Instruction Set Verification Formal Verification simple_cpu.v uart_tx.v uart_rx.v cpu_scoreboard.sv cpu_test.sv simple_cpu_buggy.v Mahatma Jyotiba Phule Rohilkhand University Accellera Systems Initiative ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard Vatsal Verma Unnati Gangwar Anuj Shakya Lalita Chauhan Janak Kapoor TLM Analysis Ports 8N1 Serial Framing Random Instruction Sequence Generation Cycle-Accurate Simulation