2026-08-05
4 items 208 entities 266 connections
Processed 87 entities and 118 relations.
LiFU CPU Fuzzing Smart Coordination Feedback-Driven Coordination Semantic Seed Triage Hybrid Mutation LLM-Guided Generative Mutation Differential Testing Asymmetric Simulation ISS Pre-Run Filtering Reachability Analysis LLM-Guided Property Generation Coverage-Guided Fuzzing Formal Verification RTL Simulation Weight Cache Seed Scoring Pipelined Fuzzing Ensemble Fuzzing Random Mutation Directed Fuzzing Dependency Chain Generation Corpus Merging Assembly Synthesis SVA Property Synthesis Grey-Box Fuzzing White-Box Fuzzing Multi-Armed Bandit RFUZZ DirectFuzz DifuzzRTL Cascade HyPFuzz GenHuzz ProcessorFuzz WhisperFuzz TheHuzz ChatFuzz RISCV-Torture Spike VCS VC Formal GPT-4-turbo Instruction Set Simulator (ISS) Micro-Architectural State Space Coverage Feedback FSM Coverage Line Coverage Condition Coverage Seed Corpus Pipeline Hazard Data Forwarding Register Dependency Large Language Model (LLM) RTL RISC-V Mismatch Detection Testcase Generation Non-Progressing Testcase Filtering Knowledge Base Instruction Diversity Poisonous Interaction Coverpoint UVM Human-in-the-Loop Triage Beyond Fuzzer Islands: CPU Fuzzing via Smart Coordination Yuchen Hu Jialin Sun Yushu Du Renshuang Jiang Ning Wang Weiwei Shan Xinwei Fang Xi Wang Nan Guan Zhe Jiang Southeast University National Center of Technology Innovation for EDA National University of Defense Technology City University of Hong Kong University of York RocketChip BOOM CVA6 Algorithm 1: Filter for Non-Progressing Testcases Algorithm 2: Reachability Analysis for Uncovered Point Algorithm 3: LLM-Guided Property Generation Non-Progressing Testcase Filtering
Processed 37 entities and 52 relations.
Spike Sail-RISC-V RVVTS RISC-V Vector Extension golden reference model positive testing negative testing coverage-guided test generation single instruction isolation failure code minimization ISA simulator executable specification formal specification functional coverage invalid instruction sequences valid instruction sequences machine state data-level parallelism riscvOVPsim RISCV-DV RISC-V Vector Tests Generator Sail-RISC-V and Spike for RISC-V Vector: Toward Consistent Golden Reference Behavior Single Instruction Isolation for RISC-V Vector Test Failures Randomized Testing of RISC-V CPUs Using Direct Instruction Injection Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side Manfred Schlägl Katharina Ruep Daniel Große Vladimir Herdt Rolf Drechsler Alexandre Joannou Johannes Kepler University Linz Design Under Test instruction validity checking vector register grouping saturation flag architectural validation
IMPLEMENTING RANDOM CONTENT OF PROGRAM LOOPS IN RANDOM TEST GENERATION FOR PROCESSOR VERIFICATION - Patent application
source →Processed 33 entities and 38 relations.
Constrained Random Test Generation Converged Branch Instruction Stream Branch-Not-Taken (BNT) Mechanism Built-In Exception Handling Mechanism Deterministic Return from Interrupt Handler Mandatory Read-Only Registers Global Class Restriction Mechanism Machine State Detection and Restoration Mechanism Random Program Loop Generation Relocatable Interrupt Handler Address Translation Exception Handling Processor Pre-Silicon Functional Verification IBM GenesysPro Constrained Random Test Generator RAVEN Test Program Generator Test Generator 110 Program Loop in Processor Verification Early Exit from Loop Storage Addressability Preservation Speculative Execution Verification Branch History Table Verification Reentrant Mode Test Generation Test Case Definition Predefined Test Definition Generation Directive International Business Machines Corporation Functional Verification of the IBM System z10 Processor Chipset Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification Reconfigurable Model-Based Test Program Generator for Microprocessors IBM z/Architecture Addressing Mode (SAM24/SAM31/SAM64) Computer Program Product for Random Loop Test Generation Olaf K. Hendrickson Processor Pre-Silicon Functional Verification
WhisperFuzz: White-Box Fuzzing for Detecting and Locating Timing Vulnerabilities in Processors
source →Processed 51 entities and 58 relations.
WhisperFuzz white-box fuzzing black-box fuzzing grey-box fuzzing hardware fuzzing Micro-Event Graph register-transfer level timing side-channel attack timing vulnerability microarchitectural state transition finite-state machine coverage-feedback fuzzing seed generation differential testing operand mutation Micro-Event Path static program analysis SystemVerilog Assertion instruction sequence generation simulation trace hierarchical leakage analysis performance counter timing coverage metric speculative execution vulnerability information-flow tracking formal verification design-under-test Zkt extension HyPFuzz VCS Chipyard RISC-V ISA BOOM Rocket Core CVA6 Pallavi Borkar Chen Chen Mohamadreza Rostami Nikhilesh Singh Rahul Kande Ahmad-Reza Sadeghi Chester Rebeiro Jeyavijayan Rajendran Indian Institute of Technology Madras Texas A&M University Technische Universität Darmstadt WhisperFuzz: White-Box Fuzzing for Detecting and Locating Timing Vulnerabilities in Processors DIVUW instruction REMW instruction cache timing behavior breadth-first search