2026-08-04
5 items 135 entities 184 connections
Processed 33 entities and 45 relations.
ChiGen Verismith VlogHammer TransFuzz Verible Verilator Yosys Jasper Formal Verification Platform Icarus Verilog ChiBench Fuzzing Probabilistic Grammar Hardware Description Language Verilog SystemVerilog SystemVerilog Assertions Formal Verification Electronic Design Automation n-gram Language Model Hindley-Milner Type Inference Scope Management Abstract Syntax Tree Generation Packages (SystemVerilog) Interfaces (SystemVerilog) Classes (SystemVerilog) Large Language Model Luiza de Melo Gomes Fernando Magno Quintão Pereira UFMG Cadence Design Systems RTL Benchmark Suite Generation of various programs in Verilog/SystemVerilog for testing EDA tools
Processed 34 entities and 57 relations.
ChiGen Verismith VlogHammer TransFuzz Yosys Verilator Verible Jasper Formal Verification Platform Icarus Verilog Fuzzing Bottom-Up Generation Probabilistic Context-Free Grammar Hindley-Milner Type Inference Code Injection Reaching Definition Analysis Variable Renaming and Scope Creation Verilog SystemVerilog Hardware Description Language Electronic Design Automation RTL ChiBench Constraint Generation and Unification Abstract Syntax Tree Skeleton Generation Cadence Design Systems UFMG Fernando Magno Quintão Pereira Code Coverage Context-Sensitive Probabilities Module Injection Lost in Translation: Enabling Confused Deputy Attacks on EDA Software with TransFuzz A General Framework for Hindley/Milner Type Systems with Constraints AddressSanitizer
Processed 42 entities and 58 relations.
SearchSYS gem5 AFL++ Differential Testing LLM-based Test Code Generation Coverage-Guided Fuzz Testing Zero-Shot Prompting Search-Based Software Testing Seed Generation Parameterized Input Generation Mutation Operators Prompt Engineering ARM Instruction Set Architecture X86 Instruction Set Architecture RISC-V ARMv8 GPT-3.5-turbo CodeLlama TinyLlama Phi2 Llama2 Magicoder CodeBooga Ollama C Token Categories for Prompt Templates Binary File Mutation Compiler Optimization Tokens Search+LLM-based Testing for ARM Simulators Karine Even-Mendoza Héctor D. Menéndez W.B. Langdon Aidan Dakhama Justyna Petke Bobby R. Bruce King's College London University College London University of California, Davis ARM Regression Testing Test Suite Minimization afl-cmin C Program Generation
Processed 2 entities and 1 relations.
Processed 24 entities and 23 relations.
RISCV-DV SystemVerilog UVM RISC-V RV32IMAFDC RV64IMAFDC Machine Mode Supervisor Mode User Mode Page Table Randomization Privileged CSR Trap and Interrupt Handling MMU Stress Testing Illegal Instruction Generation Random Instruction Generation Debug Mode Instruction Generation Coverage Model Co-simulation Spike ISS riscv-ovpsim Whisper ISS sail-riscv Google Directed Instruction Test