ChiBench

Tool

First seen 8/4/2026

Last seen 8/4/2026

Evidence 12 chunks

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ChiGen ← uses 100% 5e

ChiGen was trained on ChiBench, a collection of 50,000 Verilog designs.

Benchmark Suite implements → 100% 2e

ChiBench is a collection of Verilog programs serving as a benchmark suite for EDA tool testing.

ChiGen part of → 85% 2e

ChiBench is released alongside ChiGen as a companion training benchmark suite.

Verible uses → 95% 1e

ChiBench uses Verible's syntactic analyzer as the first sieve to filter out syntactically invalid Verilog designs.

ChiBench uses Jasper's HDL semantic analyzer as a second sieve to filter semantically invalid Verilog designs.