ChiGen
ToolFirst seen 8/4/2026
Last seen 8/4/2026
Evidence 30 chunks
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46 connectionsChiGen is compared against TransFuzz in terms of structural diversity, code coverage, and bug-finding ability.
ChiGen is compared against Verismith in terms of structural diversity, code coverage, and bug-finding ability.
ChiGen is compared against VlogHammer in terms of structural diversity, code coverage, and bug-finding ability.
ChiGen was trained on ChiBench, a collection of 50,000 Verilog designs.
ChiGen applies the Hindley-Milner type inference algorithm to infer the types of variables in generated Verilog designs.
ChiGen was originally developed to test and evaluate the Jasper Formal Verification Platform.
ChiGen was used in bug-finding campaigns on Yosys, revealing crashes and issues.
ChiGen is a fuzzer that generates random Verilog designs to test EDA tools.
ChiGen was used in bug-finding campaigns on Verilator, revealing crashes and issues.
ChiGen uncovered issues in Icarus Verilog through generated designs.
ChiGen generates some SystemVerilog syntax but does not support the full IEEE 1800-2017 SystemVerilog specification.
ChiGen was enhanced to include the generation of SystemVerilog class constructs.
ChiGen was enhanced to generate SystemVerilog assertions and formal verification primitives.
ChiGen was used to find and confirm bugs in Verible including crashes.
ChiGen uses module injection to combine multiple Verilog modules into complex designs.
ChiGen uses code injection to combine Verilog modules, functions, and references to achieve a predefined number of tokens.
ChiGen uses a Probabilistic Context-Free Grammar to generate the skeleton of Verilog designs.
ChiGen was enhanced to include the generation of SystemVerilog package constructs.
ChiGen was developed to test EDA tools by generating Verilog designs.
ChiGen generates Verilog designs through skeleton generation using a probabilistic grammar.
ChiGen uses n-gram language models to guide synthesis of Verilog programs.
ChiGen employs a dedicated scope management engine called the 'scope delimiter' to manage identifier visibility.
ChiGen produces abstract syntax trees during its generation process which are then refined.
ChiGen uses Verible's grammar as the basis for its probabilistic context-free grammar.
ChiGen was enhanced to include the generation of SystemVerilog interface constructs.
ChiGen generates Verilog designs as its core output.
ChiGen generates SystemVerilog designs including modern constructs.
ChiGen implements generation of formal verification constructs like assertions and properties.
The paper presents and uses ChiGen as its primary tool for Verilog generation and EDA testing.
ChiGen is described as a 'bottom-up' fuzzer that generates Verilog designs using bottom-up generation methodology.
ChiGen replaces mock identifiers with names that respect scoping rules using variable renaming and scope creation.
ChiGen uses context-sensitive probabilities in its probabilistic grammar to better model real Verilog syntax.
ChiGen first generates a skeleton of a Verilog design before filling in names and types.
ChiGen uses constraint generation and unification as part of the Hindley-Milner type inference process.
ChiGen was originally developed to test Cadence's Jasper platform, with Cadence engineers as co-authors.
ChiGen is evaluated in terms of code coverage it achieves when its generated designs are used as input to EDA tools.
ChiBench is released alongside ChiGen as a companion training benchmark suite.
The paper introduces enhancements to ChiGen, a Verilog fuzzer.
ChiGen generates programs in Verilog and SystemVerilog, which are hardware description languages.
Fernando Magno Quintão Pereira is listed as one of the authors of the paper presenting ChiGen and is affiliated with UFMG.
ChiGen uses reaching definition analysis to determine valid injection points for module injection.
ChiGen was developed at UFMG in collaboration with Cadence Design Systems.
ChiGen has been integrated into Cadence Design Systems' development methodology.
ChiGen is compared with LLMs for Verilog code generation, highlighting its unique advantage of probabilistic grammar-based generation.
ChiGen uses an abstract syntax tree during constraint generation for type inference.
ChiGen's bug-finding campaigns compiled EDA tools with AddressSanitizer to detect memory errors.