Verible

Tool

Verible is identified in the RISC-V DV repository documentation as the tool used to check Verilog style. The repository provides a script to install Verible and recommends running Verilog style checks and fixing violations before submitting pull requests.

First seen 5/26/2026

Last seen 8/11/2026

Evidence 15 chunks

Wiki v1

WIKI

Overview

Verible is described in the RISC-V DV repository as the tool used to check Verilog style.[1]

Use in RISC-V DV

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NEIGHBORHOOD

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RELATIONSHIPS

12 connections

ChiGen ← evaluates 100% 3e

ChiGen was used to find and confirm bugs in Verible including crashes.

ChiGen ← uses 100% 2e

ChiGen uses Verible's grammar as the basis for its probabilistic context-free grammar.

RTL evaluates → 93% 1e

Verible lints and formats RTL (SystemVerilog) code for the VeeR project.

Antmicro ← uses 97% 1e

Antmicro added Verible formatter and linting actions to the VeeR CI.

UnityChipForXiangShan ← uses 92% 1e

The Docker image for UnityChipForXiangShan includes Verible as a tool.

Docker part of → 95% 1e

The Docker image includes Verible as a bundled tool.

Hardware Description Language implements → 90% 1e

Verible is an open-source Verilog parsing and linting tool that supports Verilog HDL.

ChiBench ← uses 95% 1e

ChiBench uses Verible's syntactic analyzer as the first sieve to filter out syntactically invalid Verilog designs.

Verismith ← evaluates 90% 1e

Verismith was used in bug-finding campaigns on Verible's obfuscator as a baseline comparison to ChiGen.

riscv-dv ← uses 1e

RISCV-DV uses Verible for Verilog style checking.

TransFuzz ← evaluates 90% 1e

TransFuzz was used in bug-finding campaigns on Verible as a baseline comparison to ChiGen.

Continuous Integration uses → 95% 1e

Verible linting and formatting are integrated into CI workflows for VeeR.

LINKED ENTITIES

1 links

riscv-dv used_by The evidence is from the RISC-V DV repository and states that Verible can be installed there as the tool to check Verilog style.

CITATIONS

4 sources

4 citations — click to collapse

[1] Verible is the tool used to check Verilog style. chipsalliance/riscv-dv

[2] The RISC-V DV repository provides verilog_style/build-verible.sh as the command to install Verible. chipsalliance/riscv-dv

[3] The RISC-V DV documentation recommends running Verilog style checks and cleaning up style violations before submitting a pull request. chipsalliance/riscv-dv

[4] RISC-V DV is a SystemVerilog/UVM-based open-source instruction generator for RISC-V processor verification and requires an RTL simulator supporting SystemVerilog and UVM 1.2. chipsalliance/riscv-dv