Verible

Tool

Verible is identified in the RISC-V DV repository documentation as the tool used to check Verilog style. The repository provides a script to install Verible and recommends running Verilog style checks and fixing violations before submitting pull requests.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

Verible is described in the RISC-V DV repository as the tool used to check Verilog style.[1]

Use in RISC-V DV

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NEIGHBORHOOD

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RELATIONSHIPS

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riscv-dv ← uses 1e

RISCV-DV uses Verible for Verilog style checking.

LINKED ENTITIES

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riscv-dv used_by The evidence is from the RISC-V DV repository and states that Verible can be installed there as the tool to check Verilog style.

CITATIONS

4 sources

4 citations — click to collapse

[1] Verible is the tool used to check Verilog style. chipsalliance/riscv-dv

[2] The RISC-V DV repository provides verilog_style/build-verible.sh as the command to install Verible. chipsalliance/riscv-dv

[3] The RISC-V DV documentation recommends running Verilog style checks and cleaning up style violations before submitting a pull request. chipsalliance/riscv-dv

[4] RISC-V DV is a SystemVerilog/UVM-based open-source instruction generator for RISC-V processor verification and requires an RTL simulator supporting SystemVerilog and UVM 1.2. chipsalliance/riscv-dv