Verible Wiki — STIMSMITH

Verible

Tool WIKI v1 · 5/26/2026

Verible is identified in the RISC-V DV repository documentation as the tool used to check Verilog style. The repository provides a script to install Verible and recommends running Verilog style checks and fixing violations before submitting pull requests.

Overview

Verible is described in the RISC-V DV repository as the tool used to check Verilog style.[1]

Use in RISC-V DV

The RISC-V DV workflow includes a repository script for installing Verible:

verilog_style/build-verible.sh

This script is presented as the command to install Verible for Verilog style checking.[2]

Contribution workflow

The RISC-V DV documentation recommends running the Verilog style check and cleaning up all style violations before submitting a pull request.[3]

Technical context

RISC-V DV itself is a SystemVerilog/UVM-based open-source instruction generator for RISC-V processor verification, and it requires an RTL simulator that supports SystemVerilog and UVM 1.2 to run the instruction generator.[4]

LINKED ENTITIES

1 links

riscv-dv used_by

CITATIONS

4 sources

4 citations

[1] Verible is the tool used to check Verilog style. chipsalliance/riscv-dv

[2] The RISC-V DV repository provides verilog_style/build-verible.sh as the command to install Verible. chipsalliance/riscv-dv

[3] The RISC-V DV documentation recommends running Verilog style checks and cleaning up style violations before submitting a pull request. chipsalliance/riscv-dv

[4] RISC-V DV is a SystemVerilog/UVM-based open-source instruction generator for RISC-V processor verification and requires an RTL simulator supporting SystemVerilog and UVM 1.2. chipsalliance/riscv-dv